From e225cbd28f7c3f8fc169b4b76d0d8fca1f818178 Mon Sep 17 00:00:00 2001
From: Michael Betz <michibetz@gmail.com>
Date: Tue, 6 Oct 2020 11:35:03 -0700
Subject: [PATCH] add zedboard platform to CI

---
 litex_boards/platforms/zedboard.py | 7 +++++++
 test/test_targets.py               | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/litex_boards/platforms/zedboard.py b/litex_boards/platforms/zedboard.py
index 51b5198..0d5b88b 100644
--- a/litex_boards/platforms/zedboard.py
+++ b/litex_boards/platforms/zedboard.py
@@ -77,6 +77,13 @@ _io = [
         Subsignal("vrn", Pins("M7")),
         Subsignal("vrp", Pins("N7")),
         Subsignal("we_n", Pins("R4"))
+    ),
+
+    # serial (just to make CI pass)
+    # unfortunately the only USB UART is hard-wired to the ARM CPU
+    ("serial", 0,
+        Subsignal("tx", Pins("-")),
+        Subsignal("rx", Pins("-"))
     )
 ]
 
diff --git a/test/test_targets.py b/test/test_targets.py
index 719311e..a4bda1d 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -63,6 +63,9 @@ class TestTargets(unittest.TestCase):
         # Xilinx Kintex Ultrascale
         platforms.append("kcu105")
 
+        # Xilinx Zynq-7000
+        platforms.append("zedboard")
+
         # Xilinx Zynq Ultrascale+
         platforms.append("zcu104")