From e229d1a0b6a836b5936f33f1a05b8c0a4326d478 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 28 Dec 2023 19:48:27 +0100 Subject: [PATCH] alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66. --- litex_boards/platforms/alinx_axau15.py | 69 ++++++++++++++------------ litex_boards/targets/alinx_axau15.py | 34 ++++++------- 2 files changed, 53 insertions(+), 50 deletions(-) diff --git a/litex_boards/platforms/alinx_axau15.py b/litex_boards/platforms/alinx_axau15.py index 464c7de..8c25d1c 100644 --- a/litex_boards/platforms/alinx_axau15.py +++ b/litex_boards/platforms/alinx_axau15.py @@ -10,42 +10,43 @@ from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - # Clk / Rst - ("sys_clk200", 0, + # Clk / Rst. + ("clk200", 0, Subsignal("p", Pins("T24"), IOStandard("LVDS")), Subsignal("n", Pins("U24"), IOStandard("LVDS")) ), - ("gth_clk156", 0, + ("clk156", 0, Subsignal("p", Pins("T7"), IOStandard("LVDS")), Subsignal("n", Pins("T6"), IOStandard("LVDS")) ), - # Buttons - ("user_btn_1", 0, Pins("N26"), IOStandard("LVCMOS33")), - ("user_btn_2", 0, Pins("AA23"), IOStandard("LVCMOS33")), + # Buttons. + ("user_btn", 0, Pins("N26"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("AA23"), IOStandard("LVCMOS33")), - # Leds + # Leds. ("user_led", 0, Pins("W21"), IOStandard("LVCMOS18")), ("user_led", 1, Pins("AC16"), IOStandard("LVCMOS18")), - # Serial + # Serial. ("serial", 0, - Subsignal("tx", Pins("A13")), - Subsignal("rx", Pins("A12")), + Subsignal("tx", Pins("A13")), + Subsignal("rx", Pins("A12")), IOStandard("LVCMOS33") ), + # SDCard. ("sdcard", 0, - Subsignal("data", Pins(f"Y22 Y23 W20 W19"), Misc("PULLUP True")), - Subsignal("cmd", Pins(f"AA24"), Misc("PULLUP True")), - Subsignal("clk", Pins(f"AA25")), - Subsignal("cd", Pins(f"Y25")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS18"), + Subsignal("data", Pins("Y22 Y23 W20 W19"), Misc("PULLUP True")), + Subsignal("cmd", Pins("AA24"), Misc("PULLUP True")), + Subsignal("clk", Pins("AA25")), + Subsignal("cd", Pins("Y25")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS18"), ), - # DDR4 SDRAM MT40A512M16 + # DDR4 SDRAM MT40A512M16. ("ddram", 0, Subsignal("a", Pins( "G25 M26 L25 E26 M25 F22 H26 F24", @@ -83,6 +84,7 @@ _io = [ Misc("SLEW=FAST"), ), + # SPIFlash. ("spiflash4x", 0, Subsignal("cs_n", Pins("AA12")), Subsignal("clk", Pins("Y11")), @@ -90,7 +92,7 @@ _io = [ IOStandard("LVCMOS18") ), - # RGMII Ethernet + # RGMII Ethernet. ("eth_clocks", 0, Subsignal("tx", Pins("AE16")), Subsignal("rx", Pins("AD21")), @@ -107,7 +109,7 @@ _io = [ Subsignal("tx_data", Pins("Y18 AA18 AB24 AC24"), IOStandard("LVCMOS18")), ), - # PCIe + # PCIe. ("pcie_x1", 0, Subsignal("rst_n", Pins("T19"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB7")), @@ -243,23 +245,23 @@ _connectors = [ "LA32_N" : "AD26", } ), - # ("XADC", { - # "GPIO0" : "AB25", - # "GPIO1" : "AA25", - # "GPIO2" : "AB28", - # "GPIO3" : "AA27", - # "VAUX0_N" : "J24", - # "VAUX0_P" : "J23", - # "VAUX8_N" : "L23", - # "VAUX8_P" : "L22", - # } - # ), + ("XADC", { + "GPIO0" : "AB25", + "GPIO1" : "AA25", + "GPIO2" : "AB28", + "GPIO3" : "AA27", + "VAUX0_N" : "J24", + "VAUX0_P" : "J23", + "VAUX8_N" : "L23", + "VAUX8_P" : "L22", + } + ), ] # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxUSPPlatform): - default_clk_name = "sys_clk200" + default_clk_name = "clk200" default_clk_period = 1e9/200e6 def __init__(self, toolchain="vivado"): @@ -270,5 +272,6 @@ class Platform(XilinxUSPPlatform): def do_finalize(self, fragment): XilinxUSPPlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("sys_clk200", loose=True), 1e9/200e6) - #self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]") + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6) + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") \ No newline at end of file diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py index 307f957..4610b60 100755 --- a/litex_boards/targets/alinx_axau15.py +++ b/litex_boards/targets/alinx_axau15.py @@ -9,7 +9,6 @@ import os from migen import * -from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * @@ -29,16 +28,17 @@ from litepcie.software import generate_litepcie_software # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): - def __init__(self, platform, sys_clk_freq, with_video_pll=False): - self.rst = Signal() + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys4x = ClockDomain() self.cd_idelay = ClockDomain() - # Clk. - clk200 = platform.request("sys_clk200") - # # # + + # Clk. + clk200 = platform.request("clk200") + # PLL. self.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(self.rst) @@ -52,11 +52,11 @@ class _CRG(LiteXModule): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), - with_ethernet = False, - with_etherbone = False, - eth_ip = "192.168.1.50", - with_led_chaser = True, - with_pcie = True, + with_ethernet = False, + with_etherbone = False, + eth_ip = "192.168.1.50", + with_led_chaser = True, + with_pcie = True, **kwargs): platform = alinx_axau15.Platform() @@ -88,8 +88,8 @@ class BaseSoC(SoCCore): bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) - # TODO: add SFP+ cages for ethernet # Ethernet / Etherbone --------------------------------------------------------------------- + # TODO: add SFP+ cages for ethernet # if with_ethernet or with_etherbone: # self.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, # data_pads = self.platform.request("sfp", 0), @@ -125,11 +125,11 @@ def main(): #assert not (args.with_etherbone and args.eth_dynamic_ip) soc = BaseSoC( - sys_clk_freq = args.sys_clk_freq, - #with_ethernet = args.with_ethernet, - #with_etherbone = args.with_etherbone, - #eth_ip = args.eth_ip, - #eth_dynamic_ip = args.eth_dynamic_ip, + sys_clk_freq = args.sys_clk_freq, + #with_ethernet = args.with_ethernet, + #with_etherbone = args.with_etherbone, + #eth_ip = args.eth_ip, + #eth_dynamic_ip = args.eth_dynamic_ip, **parser.soc_argdict )