diff --git a/litex_boards/platforms/xilinx_zcu106.py b/litex_boards/platforms/xilinx_zcu106.py
new file mode 100644
index 0000000..45958ff
--- /dev/null
+++ b/litex_boards/platforms/xilinx_zcu106.py
@@ -0,0 +1,55 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst
+    ("rst",    0, Pins("G13"), IOStandard("LVCMOS18")),
+    ("clk125", 0,
+        Subsignal("p", Pins("H9"), IOStandard("DIFF_SSTL15")),
+        Subsignal("n", Pins("G9"), IOStandard("DIFF_SSTL15")),
+    ),
+
+    # Leds
+    ("user_led", 0, Pins("AL11"), IOStandard("LVCMOS12")),
+    ("user_led", 1, Pins("AL13"), IOStandard("LVCMOS12")),
+    ("user_led", 2, Pins("AK13"), IOStandard("LVCMOS12")),
+    ("user_led", 3, Pins("AE15"), IOStandard("LVCMOS12")),
+    ("user_led", 4, Pins("AM8"),  IOStandard("LVCMOS12")),
+    ("user_led", 5, Pins("AM9"),  IOStandard("LVCMOS12")),
+    ("user_led", 6, Pins("AM10"), IOStandard("LVCMOS12")),
+    ("user_led", 7, Pins("AM11"), IOStandard("LVCMOS12")),
+
+    # Serial
+    ("serial", 0,
+        Subsignal("cts", Pins("AP17")),
+        Subsignal("rts", Pins("AM15")),
+        Subsignal("tx",  Pins("AL17")),
+        Subsignal("rx",  Pins("AH17")),
+        IOStandard("LVCMOS12")
+    ),
+]
+
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(XilinxPlatform):
+    default_clk_name   = "clk125"
+    default_clk_period = 1e9/125e6
+
+    def __init__(self):
+        XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain="vivado")
+
+    def create_programmer(self):
+        return VivadoProgrammer()
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py
new file mode 100755
index 0000000..adff449
--- /dev/null
+++ b/litex_boards/targets/xilinx_zcu106.py
@@ -0,0 +1,84 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import zcu106
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
+        self.clock_domains.cd_sys = ClockDomain()
+
+        # # #
+
+        clk125 = platform.request("clk125")
+        rst    = platform.request("rst")
+
+        self.submodules.pll = pll = USMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst | ~rst)
+        pll.register_clkin(clk125, 125e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
+        platform = zcu106.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident          = "LiteX SoC on ZCU106",
+            ident_version  = True,
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on ZCU106")
+    parser.add_argument("--build",        action="store_true", help="Build bitstream.")
+    parser.add_argument("--load",         action="store_true", help="Load bitstream.")
+    parser.add_argument("--sys-clk-freq", default=125e6,       help="System clock frequency.")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        **soc_core_argdict(args)
+    )
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+if __name__ == "__main__":
+    main()