From e2a66090ee5361b4fe7fab9ec3eb4554b8448497 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Mar 2020 16:55:22 +0100 Subject: [PATCH] targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. --- litex_boards/targets/kcu105.py | 37 +++++------------------------ litex_boards/targets/mercury_xu5.py | 31 +++--------------------- litex_boards/targets/vcu118.py | 31 ++---------------------- litex_boards/targets/zcu104.py | 33 +++---------------------- 4 files changed, 14 insertions(+), 118 deletions(-) diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index f14394f..c5584bb 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -25,14 +25,13 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_ic = ClockDomain() # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) - self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) @@ -46,33 +45,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), ] - ic_reset_counter = Signal(max=64, reset=63) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(ic_reset_counter != 0, - ic_reset_counter.eq(ic_reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - ic_rdy = Signal() - ic_rdy_counter = Signal(max=64, reset=63) - self.cd_sys.rst.reset = 1 - self.comb += self.cd_ic.clk.eq(self.cd_sys.clk) - self.sync.ic += [ - If(ic_rdy, - If(ic_rdy_counter != 0, - ic_rdy_counter.eq(ic_rdy_counter - 1) - ).Else( - self.cd_sys.rst.eq(0) - ) - ) - ] - self.specials += [ - Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, - o_RDY=ic_rdy), - AsyncResetSynchronizer(self.cd_ic, ic_reset) - ] + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ @@ -89,8 +62,10 @@ class BaseSoC(SoCSDRAM): # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), - memtype = "DDR4", - sys_clk_freq = sys_clk_freq) + memtype = "DDR4", + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6, + cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) sdram_module = EDY4016A(sys_clk_freq, "1:4") diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index dc89a5a..8fb86cb 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -25,7 +25,8 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_ic = ClockDomain() + + # # # self.submodules.pll = pll = USMMCM(speedgrade=-1) pll.register_clkin(platform.request("clk100"), 100e6) @@ -42,33 +43,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), ] - ic_reset_counter = Signal(max=64, reset=63) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(ic_reset_counter != 0, - ic_reset_counter.eq(ic_reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - ic_rdy = Signal() - ic_rdy_counter = Signal(max=64, reset=63) - self.cd_sys.rst.reset = 1 - self.comb += self.cd_ic.clk.eq(self.cd_sys.clk) - self.sync.ic += [ - If(ic_rdy, - If(ic_rdy_counter != 0, - ic_rdy_counter.eq(ic_rdy_counter - 1) - ).Else( - self.cd_sys.rst.eq(0) - ) - ) - ] - self.specials += [ - Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, - o_RDY=ic_rdy), - AsyncResetSynchronizer(self.cd_ic, ic_reset) - ] + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index ac1ae26..881d7fb 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -23,14 +23,13 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_ic = ClockDomain() # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) - self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) @@ -44,33 +43,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), ] - ic_reset_counter = Signal(max=64, reset=63) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(ic_reset_counter != 0, - ic_reset_counter.eq(ic_reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - ic_rdy = Signal() - ic_rdy_counter = Signal(max=64, reset=63) - self.cd_sys.rst.reset = 1 - self.comb += self.cd_ic.clk.eq(self.cd_sys.clk) - self.sync.ic += [ - If(ic_rdy, - If(ic_rdy_counter != 0, - ic_rdy_counter.eq(ic_rdy_counter - 1) - ).Else( - self.cd_sys.rst.eq(0) - ) - ) - ] - self.specials += [ - Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, - o_RDY=ic_rdy), - AsyncResetSynchronizer(self.cd_ic, ic_reset) - ] + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 61275eb..6440ba6 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -7,7 +7,6 @@ import argparse from migen import * -from migen.genlib.io import CRG from litex_boards.platforms import zcu104 @@ -26,11 +25,11 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk500 = ClockDomain() - self.clock_domains.cd_ic = ClockDomain() + + # # # self.submodules.pll = pll = USMMCM(speedgrade=-2) pll.register_clkin(platform.request("clk125"), 125e6) - pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_clk500, 500e6, with_reset=False) @@ -43,33 +42,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_clk500, ~pll.locked), ] - ic_reset_counter = Signal(max=64, reset=63) - ic_reset = Signal(reset=1) - self.sync.clk500 += \ - If(ic_reset_counter != 0, - ic_reset_counter.eq(ic_reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - ic_rdy = Signal() - ic_rdy_counter = Signal(max=64, reset=63) - self.cd_sys.rst.reset = 1 - self.comb += self.cd_ic.clk.eq(self.cd_sys.clk) - self.sync.ic += [ - If(ic_rdy, - If(ic_rdy_counter != 0, - ic_rdy_counter.eq(ic_rdy_counter - 1) - ).Else( - self.cd_sys.rst.eq(0) - ) - ) - ] - self.specials += [ - Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk500"), i_RST=ic_reset, - o_RDY=ic_rdy), - AsyncResetSynchronizer(self.cd_ic, ic_reset) - ] + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------