diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
index 69406ef..c5b397d 100755
--- a/litex_boards/targets/lattice_crosslink_nx_evn.py
+++ b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -63,7 +63,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    SoCCore.mem_map = {
+    mem_map = {
         "rom":              0x00000000,
         "sram":             0x40000000,
         "csr":              0xf0000000,
diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py
index a44e6d7..13f6683 100755
--- a/litex_boards/targets/lattice_crosslink_nx_vip.py
+++ b/litex_boards/targets/lattice_crosslink_nx_vip.py
@@ -64,7 +64,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    SoCCore.mem_map = {
+    mem_map = {
         "rom":              0x00000000,
         "sram":             0x40000000,
         "csr":              0xf0000000,