From e44e63f65da92410894ddcc937e173136db5e799 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 13 Oct 2022 19:48:41 +0200 Subject: [PATCH] targets/digilent_arty_z7: add flash region --- litex_boards/targets/digilent_arty_z7.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 70d4085..5d2a96b 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -84,6 +84,7 @@ class BaseSoC(SoCCore): wishbone = wb_gp0, base_address = self.mem_map["csr"]) self.bus.add_master(master=wb_gp0) + self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx")) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: