diff --git a/litex_boards/platforms/colorlight_i9plus.py b/litex_boards/platforms/colorlight_i9plus.py
index c28e884..bb386e4 100644
--- a/litex_boards/platforms/colorlight_i9plus.py
+++ b/litex_boards/platforms/colorlight_i9plus.py
@@ -6,7 +6,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import Xilinx7SeriesPlatform
-from litex.build.openocd import OpenOCD
+from litex.build.openfpgaloader import OpenFPGALoader
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -127,8 +127,8 @@ class Platform(Xilinx7SeriesPlatform):
              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
 
-    def create_programmer(self, cfg="openocd_xc7_ft2232.cfg"):
-        return OpenOCD(cfg, "bscan_spi_xc7a50t.bit")
+    def create_programmer(self):
+        return OpenFPGALoader(cable="ch347_jtag")
 
     def do_finalize(self, fragment):
         Xilinx7SeriesPlatform.do_finalize(self, fragment)
diff --git a/litex_boards/targets/colorlight_i9plus.py b/litex_boards/targets/colorlight_i9plus.py
index 28df1bf..0770abf 100755
--- a/litex_boards/targets/colorlight_i9plus.py
+++ b/litex_boards/targets/colorlight_i9plus.py
@@ -179,11 +179,11 @@ def main():
         builder.build(**parser.toolchain_argdict)
 
     if args.load:
-        prog = soc.platform.create_programmer(cfg="prog/openocd_xc7_ft2232.cfg")
+        prog = soc.platform.create_programmer()
         prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
 
     if args.flash:
-        prog = soc.platform.create_programmer(cfg="prog/openocd_xc7_ft2232.cfg")
+        prog = soc.platform.create_programmer()
         prog.flash(0, builder.get_bitstream_filename(mode="flash"))
 
 if __name__ == "__main__":