From e4ccfcfad1c79d80a92034c578d093c244743eab Mon Sep 17 00:00:00 2001
From: Vamsi K Vytla <vkvytla@lbl.gov>
Date: Fri, 8 May 2020 17:20:14 -0700
Subject: [PATCH] platforms/marblemini.py: Cleanup. Add openocd for programming
 marblemini

---
 litex_boards/platforms/marblemini.py     | 24 +++++++-------
 litex_boards/prog/openocd_marblemini.cfg | 41 ++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 13 deletions(-)
 create mode 100644 litex_boards/prog/openocd_marblemini.cfg

diff --git a/litex_boards/platforms/marblemini.py b/litex_boards/platforms/marblemini.py
index af43831..2c3f7d0 100644
--- a/litex_boards/platforms/marblemini.py
+++ b/litex_boards/platforms/marblemini.py
@@ -1,5 +1,6 @@
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -14,15 +15,18 @@ _io = [
     ("mgt_clk_0", 0,
      Subsignal("p", Pins("F6")),
      Subsignal("n", Pins("E6"))),
+
     ("mgt_clk_1", 0,
      Subsignal("p", Pins("F10")),
      Subsignal("n", Pins("E10"))),
+
     ("serial", 0,
         Subsignal("rts", Pins("W9")),
         Subsignal("rx", Pins("U7")),
         Subsignal("tx", Pins("Y9")),
         IOStandard("LVCMOS25")
     ),
+
     ("eth_clocks", 0,
      Subsignal("tx", Pins("J15"), Misc("SLEW=FAST")),
      Subsignal("rx", Pins("L19")),
@@ -33,16 +37,19 @@ _io = [
      Subsignal("tx_data", Pins("G15 G16 G13 H13"), Misc("SLEW=FAST")),
      Subsignal("rst_n", Pins("M17")), IOStandard("LVCMOS25"),
      ),
+
     ("pmod", 0,
      Subsignal("pmod", Pins("C18 D22 E22 G21 D21 E21 F21 G22"), IOStandard("LVCMOS33"))),
     ("pmod", 1,
      Subsignal("pmod", Pins("F13 C14 C15 D16 F14 F15 F16 E16"), IOStandard("LVCMOS33"))),
+
     # ("sfp", 0,
     #     Subsignal("txp", Pins("AC10")),
     #     Subsignal("txn", Pins("AD10")),
     #     Subsignal("rxp", Pins("AC12")),
     #     Subsignal("rxn", Pins("AD12")),
     # ),
+
     ("ddram",
         0,
         Subsignal("a",
@@ -52,7 +59,7 @@ _io = [
         Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
         Subsignal("cas_n", Pins("J6"), IOStandard("SSTL135")),
         Subsignal("we_n", Pins("K3"),  IOStandard("SSTL135")),
-     # Subsignal("cs_n", Pins("T3"), IOStandard("SSTL135")),  # TODO: couldn't find chip select on Marble
+        # Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),  # TODO: couldn't find chip select on Marble
         Subsignal("dm", Pins("G2 E2"), IOStandard("SSTL135")),
         Subsignal("dq",
                   Pins("G3 J1 H4 H5 H2 K1 H3 J5", "G1 B1 F1 F3 C2 A1 D2 B2"),
@@ -236,18 +243,9 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
 
     def create_programmer(self):
-        # TODO: Should be changed to xc3sprog if confirmed so
-        return VivadoProgrammer()
+        return OpenOCD("openocd_marblemini.cfg")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(
-                self.lookup_request("clk20_vcxo"), 1e9 / 20e6)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(
-                self.lookup_request("mgt_clk_0"), 1e9 / 125e6)
-        except ConstraintError:
-            pass
+        self.add_period_constraint(self.lookup_request("clk20_vcxo", loose=True), 1e9 / 20e6)
+        self.add_period_constraint(self.lookup_request("mgt_clk_0", loose=True), 1e9 / 125e6)
diff --git a/litex_boards/prog/openocd_marblemini.cfg b/litex_boards/prog/openocd_marblemini.cfg
new file mode 100644
index 0000000..807b2b7
--- /dev/null
+++ b/litex_boards/prog/openocd_marblemini.cfg
@@ -0,0 +1,41 @@
+# openocd config file for Marble Mini
+# https://github.com/BerkeleyLab/Marble-mini
+
+interface ftdi
+
+# This string needs programming into U21 EEPROM attached to U23 FT4232H
+# ftdi_device_desc "Marble Mini"
+
+# Pin assignment consistent with MPSSE Channel A, Table 3.14 for FT4232H-56Q
+#  ADBUS0 (pin 12) USB_TCK
+#  ADBUS1 (pin 13) USB_TDI
+#  ADBUS2 (pin 14) USB_TDO
+#  ADBUS3 (pin 15) USB_TMS
+# Additional pin, GPIOL0, set high
+#  ADBUS4 (pin 17) EN_USB_JTAG
+# check logic of EN_USB_JTAG:
+#  routed to U39-3 P0_2 for informational purposes
+#  also to Q5, forces disable of Self_FPGA_* buffers
+
+# Default for FT4232H
+ftdi_vid_pid 0x0403 0x6011
+
+# Choose channel for FPGA JTAG, 0 == Channel A?
+ftdi_channel 0
+
+# Just TCK TDI TDO TMS, all other pins driven high.
+# Not sure what controls DBUS banks C, D, and maybe even B.
+ftdi_layout_init 0xfff8 0xfffb
+reset_config none
+
+# default speed
+adapter_khz 15000
+
+# Cribbed from openocd-code/tcl/board/kasli.cfg
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+# Following lines found in git head, but don't work with older openocd
+# version 0.10.0 available with apt-get in Debian Buster.
+# source [find fpga/xilinx-xadc.cfg]
+# source [find fpga/xilinx-dna.cfg]