From e5a144e9cd3b1c1f1711c2863f36dabd88540b4a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 19 Sep 2020 23:28:34 +0200 Subject: [PATCH] platforms/xcu1525: update ddram0 pinout. Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc. --- litex_boards/platforms/xcu1525.py | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/litex_boards/platforms/xcu1525.py b/litex_boards/platforms/xcu1525.py index e98206d..31e257e 100644 --- a/litex_boards/platforms/xcu1525.py +++ b/litex_boards/platforms/xcu1525.py @@ -78,37 +78,36 @@ _io = [ Subsignal("act_n", Pins("BB39"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")), Subsignal("bg", Pins("BC37 BC39"), IOStandard("SSTL12_DCI")), - Subsignal("cas_n", Pins("AP36"), IOStandard("SSTL12_DCI")), + Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")), # A16 + Subsignal("cas_n", Pins("AP36"), IOStandard("SSTL12_DCI")), # A15 + Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")), # A14 Subsignal("cke", Pins("BC38"), IOStandard("SSTL12_DCI")), Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")), - Subsignal("dm", Pins("AM31 AP30 AL28 AR30 AU29 AY27 BE35 BE31"), + Subsignal("dm", Pins("BC31 AY27 BB26 BD26 AP30 BF39 AR30 BA32"), IOStandard("POD12_DCI")), Subsignal("dq", Pins( - "AW28 AW29 BA28 BA27 BB29 BA29 BC27 BB27", - "BE28 BF28 BE30 BD30 BF27 BE27 BF30 BF29", - "BB31 BB32 AY32 AY33 BC32 BC33 BB34 BC34", - "AV31 AV32 AV34 AW34 AW31 AY31 BA35 BA34", - "AL30 AM30 AU32 AT32 AN31 AN32 AR32 AR31", - "AP29 AP28 AN27 AM27 AN29 AM29 AR27 AR28", - "AT28 AV27 AU27 AT27 AV29 AY30 AW30 AV28", - "BD34 BD33 BE33 BD35 BF32 BF33 BF34 BF35"), + "BB31 BB32 AY33 AY32 BC33 BC32 BB34 BC34", + "AT28 AT27 AU27 AV27 AV28 AV29 AW30 AY30", + "BA28 BA27 AW28 AW29 BC27 BB27 BA29 BB29", + "BE28 BF28 BE30 BD30 BF27 BE27 BF29 BF30", + "AT32 AU32 AM30 AL30 AR31 AN31 AR32 AN32", + "BD40 BD39 BF42 BF43 BF41 BE40 BE37 BF37", + "AM27 AN27 AP28 AP29 AM29 AN29 AR28 AR27", + "AW34 AV32 AV31 AV34 BA35 BA34 AW31 AY31"), IOStandard("POD12_DCI"), Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), - Subsignal("dqs_n", Pins("BB30 BC26 BD29 BE26 BB36 BD31 AW33 BA33"), + Subsignal("dqs_n", Pins("BB36 AU30 BB30 BD29 AM32 BF38 AL29 AW33"), IOStandard("DIFF_POD12"), Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), - Subsignal("dqs_p", Pins("BA30 BB26 BD28 BD26 BB35 BC31 AV33 BA32"), + Subsignal("dqs_p", Pins("BB35 AU2 BA30 BD28 AM31 BE38 AL28 AV33"), IOStandard("DIFF_POD12"), - Misc("PRE_EMPHASIS=RDRV_240"), Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")), - Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")), Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")), - Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")), Misc("SLEW=FAST") ), ("ddram", 1,