From e7d00a8c4329115a1fb90a523e13b04db281a93f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Aug 2024 12:35:39 +0200 Subject: [PATCH] ti60_f225_dev_kit: Update to new HyperRAM core with 2:1 ratio. Tested at up to 250MHz sys_clk -> 125MHz HyperRAM Clk. --- .../efinix_titanium_ti60_f225_dev_kit.py | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index f78203e..6cabd5c 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -27,8 +27,10 @@ from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.rst = Signal() - self.cd_sys = ClockDomain() + self.rst = Signal() + self.cd_sys = ClockDomain() + self.cd_sys2x = ClockDomain() + self.cd_sys2x_ps = ClockDomain() # # # @@ -43,8 +45,9 @@ class _CRG(LiteXModule): # (integer) of the reference clock. If all your system clocks do not fall within # this range, you should dedicate one unused clock for CLKOUT0. pll.create_clkout(None, 25e6) - - pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) + pll.create_clkout(self.cd_sys, sys_clk_freq, phase=0, with_reset=True) + pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq, phase=0, with_reset=True) + pll.create_clkout(self.cd_sys2x_ps, 2 * sys_clk_freq, phase=315, with_reset=True) # BaseSoC ------------------------------------------------------------------------------------------ @@ -93,7 +96,14 @@ class BaseSoC(SoCCore): self.add_config("L2_SIZE", hyperram_cache_size) # HyperRAM Core. - self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, latency_mode="variable", sys_clk_freq=sys_clk_freq) + self.hyperram = HyperRAM( + pads = platform.request("hyperram"), + latency = 7, + latency_mode = "variable", + sys_clk_freq = sys_clk_freq, + clk_ratio = "2:1", + dq_i_cd = "sys2x_ps", + ) self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus) # Ethernet / Etherbone ---------------------------------------------------------------------