From e94c6c8f27250774bcaf1b24cea4c4e40ca0599d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 12 Sep 2019 09:52:13 +0200 Subject: [PATCH] partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16) --- litex_boards/partner/platforms/netv2.py | 40 ++++++++++++------------- litex_boards/partner/targets/netv2.py | 4 +-- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/litex_boards/partner/platforms/netv2.py b/litex_boards/partner/platforms/netv2.py index ed63129..786dee3 100644 --- a/litex_boards/partner/platforms/netv2.py +++ b/litex_boards/partner/platforms/netv2.py @@ -46,28 +46,28 @@ _io = [ ("ddram", 0, Subsignal("a", Pins( "U6 V4 W5 V5 AA1 Y2 AB1 AB3", - "AB2 Y3 W6 Y1 V2 AA3" - ), - IOStandard("SSTL15")), - Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")), - Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")), + "AB2 Y3 W6 Y1 V2 AA3"), + IOStandard("SSTL15_R")), + Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")), + Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")), + Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")), + Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")), + Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")), Subsignal("dq", Pins( - "N2 M6 P1 N5 P2 N4 R1 P6 " - "K3 M2 K4 M3 J6 L5 J4 K6 " - ), - IOStandard("SSTL15"), - Misc("IN_TERM=UNTUNED_SPLIT_50")), - Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")), - Subsignal("odt", Pins("W9"), IOStandard("SSTL15")), + "C2 F1 B1 F3 A1 D2 B2 E2", + "J5 H3 K1 H2 J1 G2 H5 G3", + "N2 M6 P1 N5 P2 N4 R1 P6", + "K3 M2 K4 M3 J6 L5 J4 K6"), + IOStandard("SSTL15_R"), + Misc("IN_TERM=UNTUNED_SPLIT_40")), + Subsignal("dqs_p", Pins("E1 K2 P5 M1"), IOStandard("DIFF_SSTL15_R")), + Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")), + Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")), + Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")), + Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")), + Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")), Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")), - Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")), Misc("SLEW=FAST"), ), diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index 554b410..ec49dac 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -13,7 +13,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.modules import MT41J128M16 +from litedram.modules import K4B2G1646F from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII @@ -62,7 +62,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - sdram_module = MT41J128M16(sys_clk_freq, "1:4") + sdram_module = K4B2G1646F(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)