parent
3b8c55802f
commit
eb43cd3ca9
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@ -86,12 +86,12 @@ class BaseSoC(SoCCore):
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# Use EMCU's SRAM.
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# Use EMCU's SRAM.
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self.bus.add_region("sram", SoCRegion(
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self.bus.add_region("sram", SoCRegion(
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origin = self.cpu.mem_map["sram"],
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origin = self.cpu.mem_map["sram"],
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size = 16 * kB,
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size = 16 * KILOBYTE,
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))
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))
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# Use ECMU's FLASH as ROM.
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# Use ECMU's FLASH as ROM.
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self.bus.add_region("rom", SoCRegion(
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self.bus.add_region("rom", SoCRegion(
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origin = self.cpu.mem_map["rom"],
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origin = self.cpu.mem_map["rom"],
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size = 32 * kB,
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size = 32 * KILOBYTE,
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linker = True,
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linker = True,
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))
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))
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# No Gowin EMCU ----------------------------------------------------------------------------
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# No Gowin EMCU ----------------------------------------------------------------------------
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