diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py
index 433e237..777138b 100755
--- a/litex_boards/targets/de10nano.py
+++ b/litex_boards/targets/de10nano.py
@@ -76,6 +76,7 @@ class BaseSoC(SoCCore):
         # SDR SDRAM --------------------------------------------------------------------------------
         if with_mister_sdram and not self.integrated_main_ram_size:
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
+            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
                 module                  = AS4C32M16(sys_clk_freq, sdram_rate),