diff --git a/litex_boards/platforms/decklink_intensity_pro_4k.py b/litex_boards/platforms/decklink_intensity_pro_4k.py new file mode 100644 index 0000000..6a919e1 --- /dev/null +++ b/litex_boards/platforms/decklink_intensity_pro_4k.py @@ -0,0 +1,67 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst. + + # TODO. + + # Debug. + ("debug", 0, Pins("R22"), IOStandard("LVCMOS33")), + ("debug", 1, Pins("P21"), IOStandard("LVCMOS33")), + ("debug", 2, Pins("P23"), IOStandard("LVCMOS33")), + ("debug", 3, Pins("N23"), IOStandard("LVCMOS33")), + + # Fan. + ("fan", 0, Pins("K18"), IOStandard("LVCMOS33")), + + # Flash. + ("flash_cs_n", 0, Pins("C23"), IOStandard("LVCMOS33")), + ("flash", 0, + Subsignal("mosi", Pins("B24")), + Subsignal("miso", Pins("A25")), + Subsignal("vpp", Pins("B22")), + Subsignal("hold", Pins("A22")), + IOStandard("LVCMOS33") + ), + + # PCIe. + ("pcie_x4", 0, + Subsignal("rst_n", Pins("K15"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("K6")), + Subsignal("clk_n", Pins("K5")), + Subsignal("rx_p", Pins("J4 L4 N4 R4")), + Subsignal("rx_n", Pins("J3 L3 N3 R3")), + Subsignal("tx_p", Pins("H2 K2 M2 P2")), + Subsignal("tx_n", Pins("H1 K1 M1 P1")) + ), + + # HDMI Out. + + # TODO. + + # HDMI In. + + # TODO. +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + def __init__(self): + XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain="vivado") + + def create_programmer(self): + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a70t.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py new file mode 100755 index 0000000..ba377b8 --- /dev/null +++ b/litex_boards/targets/decklink_intensity_pro_4k.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * + +from litex_boards.platforms import intensity_pro_4k +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict + +from litex.soc.cores.clock import * +from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + + # # # + + self.submodules.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(ResetSignal("pcie")) + pll.register_clkin(ClockSignal("pcie"), 125e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): + platform = intensity_pro_4k.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + kwargs["uart_name"] = "crossover" + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Blackmagic Decklink Intensity Pro 4K", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC Blackmagic Decklink Intensity Pro 4K.") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + builder_args(parser) + soc_core_args(parser) + vivado_build_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder_kwargs = vivado_build_argdict(args) + builder.build(**builder_kwargs, run=args.build) + + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main()