From 05ef1ee09e8d810d351a91a54be461b6cd249f29 Mon Sep 17 00:00:00 2001 From: Fabien Date: Mon, 16 Jan 2023 13:41:24 +0100 Subject: [PATCH] Target/Platform Papilio Pro added (with Arcade MegaWing) --- .../platforms/gadgetfactory_papilio_pro.py | 123 ++++++++++++++++++ .../targets/gadgetfactory_papilio_pro.py | 122 +++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 litex_boards/platforms/gadgetfactory_papilio_pro.py create mode 100755 litex_boards/targets/gadgetfactory_papilio_pro.py diff --git a/litex_boards/platforms/gadgetfactory_papilio_pro.py b/litex_boards/platforms/gadgetfactory_papilio_pro.py new file mode 100644 index 0000000..41b8906 --- /dev/null +++ b/litex_boards/platforms/gadgetfactory_papilio_pro.py @@ -0,0 +1,123 @@ +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxSpartan6Platform +from litex.build.xilinx.programmer import XC3SProg + + +_io = [ + ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), + + ("serial", 1, + Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("spiflash", 0, + Subsignal("cs_n", Pins("P38")), + Subsignal("clk", Pins("P70")), + Subsignal("mosi", Pins("P64")), + Subsignal("miso", Pins("P65"), Misc("PULLUP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + ("spiflash2x", 0, + Subsignal("cs_n", Pins("P38")), + Subsignal("clk", Pins("P70")), + Subsignal("dq", Pins("P64", "P65")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + ("sdram", 0, + Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", + "P43 P41 P40 P141 P35 P34")), + Subsignal("ba", Pins("P143 P142")), + Subsignal("cs_n", Pins("P1")), + Subsignal("cke", Pins("P33")), + Subsignal("ras_n", Pins("P2")), + Subsignal("cas_n", Pins("P5")), + Subsignal("we_n", Pins("P6")), + Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), + Subsignal("dm", Pins("P7 P17")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ) +] + +_connectors = [ + # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + ("A", "P48 P51 P56 P58 P61 P66 P67 P75 P79 P81 P83 P85 P88 P93 P98 P100"), + ("B", "P99 P97 P92 P87 P84 P82 P80 P78 P74 P95 P62 P59 P57 P55 P50 P47"), + ("C", "P114 P115 P116 P117 P118 P119 P120 P121 P123 P124 P126 P127 P131 P132 P133 P134") + # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +] + +# Extensions -------------------------------------------------------------------------------------- + +# Arcade MegaWing V1.3 pinout +_arcade_megawing = [ + # VGA + ("vga", 0, + Subsignal("r", Pins("C:4 C:5 C:6 C:7")), + Subsignal("g", Pins("B:4 B:5 B:6 B:7")), + Subsignal("b", Pins("B:0 B:1 B:2 B:3")), + Subsignal("vsync_n", Pins("C:2")), + Subsignal("hsync_n", Pins("C:3")), + IOStandard("LVCMOS33") + ), + # Buttons + ("buttons", 0, + Subsignal("up", Pins("C:8")), + Subsignal("down", Pins("C:10")), + Subsignal("left", Pins("C:11")), + Subsignal("right", Pins("C:13")), + IOStandard("LVCMOS33") + ), + # Joysticks ports + ("joy", 0, + Subsignal("up", Pins("C:8")), + Subsignal("down", Pins("C:10")), + Subsignal("left", Pins("C:11")), + Subsignal("right", Pins("C:13")), + Subsignal("fire1", Pins("C:9")), + Subsignal("fire2", Pins("C:15")), + IOStandard("LVCMOS33") + ), + ("joy", 1, + Subsignal("up", Pins("B:12")), + Subsignal("down", Pins("B:14")), + Subsignal("left", Pins("B:15")), + Subsignal("right", Pins("A:1")), + Subsignal("fire1", Pins("B:13")), + Subsignal("fire2", Pins("A:3")), + IOStandard("LVCMOS33") + ), + # ps2 port + ("ps2", 0, + Subsignal("clk", Pins("C:1")), + Subsignal("data", Pins("C:0")), + IOStandard("LVCMOS33") + ), + ("ps2", 1, + Subsignal("clk", Pins("A:13")), + Subsignal("data", Pins("A:12")), + IOStandard("LVCMOS33") + ), + # LEDs + ("amw_user_led", 0, Pins("A:7"), IOStandard("LVCMOS33")), + ("amw_user_led", 1, Pins("A:6"), IOStandard("LVCMOS33")), + ("amw_user_led", 2, Pins("A:5"), IOStandard("LVCMOS33")), + ("amw_user_led", 3, Pins("A:4"), IOStandard("LVCMOS33")), + + # Reset button + ("reset_button", 0, Pins("P85"), IOStandard("LVCMOS33") ) +] + +class Platform(XilinxSpartan6Platform): + default_clk_name = "clk32" + default_clk_period = 31.25 + + def __init__(self, toolchain="ise"): + XilinxSpartan6Platform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors, toolchain=toolchain) + + def create_programmer(self): + return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") diff --git a/litex_boards/targets/gadgetfactory_papilio_pro.py b/litex_boards/targets/gadgetfactory_papilio_pro.py new file mode 100755 index 0000000..c2dfbc0 --- /dev/null +++ b/litex_boards/targets/gadgetfactory_papilio_pro.py @@ -0,0 +1,122 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2023 Fabien Caura +# SPDX-License-Identifier: BSD-2-Clause + +import argparse + +from migen import * + +from litex.gen import LiteXModule + +from litex.build.io import DDROutput + +from litex_boards.platforms import gadgetfactory_papilio_pro + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.video import VideoVGAPHY +from litex.soc.cores.led import LedChaser + +from litedram.modules import MT48LC4M16 +from litedram.phy import s6ddrphy, GENSDRPHY, HalfRateGENSDRPHY + +class _CRG(LiteXModule): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): + self.rst = Signal() + self.cd_sys = ClockDomain() + if sdram_rate == "1:2": + self.cd_sys2x = ClockDomain() + self.cd_sys2x_ps = ClockDomain() + else: + self.cd_sys_ps = ClockDomain() + self.cd_vga = ClockDomain() + + # # # + + # Clk / Rst + clk32 = platform.request("clk32") + + # PLL + self.pll = pll = S6PLL(speedgrade=-1) + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(clk32, 32e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + + pll.create_clkout(self.cd_vga, 40e6) + + # SDRAM clock + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) + +### BaseSoC + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=80e6, + with_led_chaser=True, + with_video_terminal = False, + **kwargs): + platform = gadgetfactory_papilio_pro.Platform() + + # CRG -------------------------------------------------------------------------------------- + self.crg = _CRG(platform, sys_clk_freq) + + # SoCCore ---------------------------------------------------------------------------------- + if kwargs.get("cpu_type", "vexriscv") == "vexriscv": + kwargs["cpu_variant"] = "minimal" + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Papilio Pro", **kwargs) + + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + sdrphy_cls = GENSDRPHY + self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) + self.add_sdram("sdram", + phy = self.sdrphy, + module = MT48LC4M16(sys_clk_freq, "1:2"), + l2_cache_size = 0 + ) + + # LEDs ------------------------------------------------------------------------------------- + if with_led_chaser: + self.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + + # Video Terminal + if with_video_terminal: + self.platform.add_extension(gadgetfactory_papilio_pro._arcade_megawing) + self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") + self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") + +def main(): + from litex.build.parser import LiteXArgumentParser + parser = LiteXArgumentParser(platform=gadgetfactory_papilio_pro.Platform(), + description="LiteX SoC on Papilio Pro") + parser.add_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.") + parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = args.sys_clk_freq, + with_video_terminal = args.with_video_terminal, + **parser.soc_argdict + ) + builder = Builder(soc, **parser.builder_argdict) + if args.build: + builder.build(**parser.toolchain_argdict) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) + +if __name__ == "__main__": + main()