From ec7a5c4c0be524fb5f7a608c2ac1a948059eca47 Mon Sep 17 00:00:00 2001 From: Do Viet Thanh Date: Tue, 14 Feb 2023 06:40:12 +0700 Subject: [PATCH] Correct DDR4 IO Banks of Xilinx Alveo U200 --- litex_boards/platforms/xilinx_alveo_u200.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/litex_boards/platforms/xilinx_alveo_u200.py b/litex_boards/platforms/xilinx_alveo_u200.py index c15af7a..4d974f8 100644 --- a/litex_boards/platforms/xilinx_alveo_u200.py +++ b/litex_boards/platforms/xilinx_alveo_u200.py @@ -349,18 +349,18 @@ class Platform(Xilinx7SeriesPlatform): # Reduce programming time self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]") # DDR4 memory channel C1 Internal Vref - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 61]") - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 62]") - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 63]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 40]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 41]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 42]") # DDR4 memory channel C2 Internal Vref self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]") # DDR4 memory channel C3 Internal Vref - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 47]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 48]") + # DDR4 memory channel C4 Internal Vref self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]") - # DDR4 memory channel C4 Internal Vref self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]") - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 73]") - self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 74]")