From ed67b91fcc8a0f8b4e68f00daff8cba35b6df02d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 14 Nov 2021 09:26:29 +0100
Subject: [PATCH] quicklogic_quickfeather: Simplify cpu_type switch between
 None/EOS-S3.

---
 litex_boards/targets/quicklogic_quickfeather.py | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py
index f452590..ee34cef 100755
--- a/litex_boards/targets/quicklogic_quickfeather.py
+++ b/litex_boards/targets/quicklogic_quickfeather.py
@@ -23,18 +23,19 @@ from litex.soc.cores.gpio import *
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, is_eoss3_cpu=False):
+    def __init__(self, platform, with_eos_s3=False):
         self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
 
         # # #
 
-        class Open(Signal): pass
-
-        if is_eoss3_cpu:
+        if with_eos_s3:
+            # Use clocks generated by the EOS-S3 CPU.
             self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
             self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
         else:
+            # Use clocks generated by the qlal4s3b_cell_macro.
+            class Open(Signal): pass
             self.specials += Instance("qlal4s3b_cell_macro",
                 o_Sys_Clk0     = self.cd_sys.clk,
                 o_Sys_Clk0_Rst = self.cd_sys.rst,
@@ -49,11 +50,7 @@ class BaseSoC(SoCCore):
         platform = quicklogic_quickfeather.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
-        if kwargs.get("cpu_type", None) == "eos-s3":
-            is_eoss3_cpu = True
-        else:
-            is_eoss3_cpu = False
-            kwargs["cpu_type"]  = None
+        kwargs["cpu_type"] = kwargs.get("cpu_type", None)
         kwargs["with_uart"] = False
         SoCCore.__init__(self, platform, sys_clk_freq,
             ident          = "LiteX SoC on QuickLogic QuickFeather",
@@ -61,7 +58,7 @@ class BaseSoC(SoCCore):
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, is_eoss3_cpu)
+        self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos-s3")
 
         # GPIOIn -> interrupt test
         if with_gpioin: