diff --git a/litex_boards/targets/alchitry_cu.py b/litex_boards/targets/alchitry_cu.py
index 7c7d92b..2d66e92 100755
--- a/litex_boards/targets/alchitry_cu.py
+++ b/litex_boards/targets/alchitry_cu.py
@@ -20,10 +20,6 @@ from litex.soc.cores.led import LedChaser
 
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-kB = 1024
-mB = 1024*kB
-
-
 # CRG -------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -80,7 +76,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 256*kB,
+            size   = 256 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py
index 3606bcf..f75eab6 100755
--- a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py
+++ b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py
@@ -25,9 +25,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -80,11 +77,11 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Antmicro SDI MIPI Video Converter Board", **kwargs)
 
         # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
-        self.spram = NXLRAM(32, 64*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
+        self.spram = NXLRAM(32, 64 * KILOBYTE)
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16 * KILOBYTE))
 
-        self.main_ram = NXLRAM(32, 64*kB)
-        self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
+        self.main_ram = NXLRAM(32, 64 * KILOBYTE)
+        self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64 * KILOBYTE))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py
index a9852e5..4a7424b 100755
--- a/litex_boards/targets/digilent_cmod_a7.py
+++ b/litex_boards/targets/digilent_cmod_a7.py
@@ -23,8 +23,7 @@ from litex.soc.interconnect import wishbone
 
 from litex.soc.integration.soc import colorer
 
-kB = 1024
-mB = 1024*kB
+# CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py
index df58150..528ca3a 100755
--- a/litex_boards/targets/efinix_t8f81_dev_kit.py
+++ b/litex_boards/targets/efinix_t8f81_dev_kit.py
@@ -22,9 +22,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -68,7 +65,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py
index 700d79c..1dfcc5c 100755
--- a/litex_boards/targets/efinix_xyloni_dev_kit.py
+++ b/litex_boards/targets/efinix_xyloni_dev_kit.py
@@ -21,9 +21,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -67,7 +64,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/fpgawars_alhambra2.py b/litex_boards/targets/fpgawars_alhambra2.py
index 40d8a20..a2ad120 100755
--- a/litex_boards/targets/fpgawars_alhambra2.py
+++ b/litex_boards/targets/fpgawars_alhambra2.py
@@ -20,8 +20,7 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
+# CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
@@ -44,6 +43,8 @@ class _CRG(LiteXModule):
         self.comb += self.cd_sys.clk.eq(sys)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done)
 
+# BaseSoC ------------------------------------------------------------------------------------------
+
 class BaseSoC(SoCCore):
 
     def __init__(self, sys_clk_freq=12e6, with_led_chaser=True, bios_flash_offset=0x50000, **kwargs):
@@ -59,7 +60,7 @@ class BaseSoC(SoCCore):
         self.add_spi_flash(mode='1x', module=N25Q032A(Codes.READ_1_1_1), with_master=False)
         self.bus.add_region("rom", SoCRegion(
             origin=self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size=32*kB,
+            size=32 * KILOBYTE,
             linker=True
         ))
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/ice_v_wireless.py b/litex_boards/targets/ice_v_wireless.py
index 9ae8e07..67ef459 100755
--- a/litex_boards/targets/ice_v_wireless.py
+++ b/litex_boards/targets/ice_v_wireless.py
@@ -28,11 +28,7 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-
-kB = 1024
-mB = 1024*kB
-
-# PSRAM flash emulation ----------------------------------------------------------------------------------------------
+# PSRAM flash emulation ----------------------------------------------------------------------------
 
 from litespi.spi_nor_flash_module import SpiNorFlashModule
 from litespi.opcodes import SpiNorFlashOpCodes as Codes
@@ -137,17 +133,17 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ICE-V Wireless", **kwargs)
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
-        self.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.spram = Up5kSPRAM(size=128 * KILOBYTE)
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 0*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
         )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 64*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 64 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
             )
 
@@ -164,7 +160,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py
index f92003a..2c93c12 100755
--- a/litex_boards/targets/icebreaker.py
+++ b/litex_boards/targets/icebreaker.py
@@ -32,9 +32,6 @@ from litex.soc.integration.builder import *
 from litex.soc.cores.video import VideoDVIPHY
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -84,17 +81,17 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on iCEBreaker", **kwargs)
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
-        self.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.spram = Up5kSPRAM(size=128 * KILOBYTE)
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 0*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
         )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 64*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 64 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
             )
 
@@ -106,7 +103,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/icebreaker_bitsy.py b/litex_boards/targets/icebreaker_bitsy.py
index 27534bd..9dce4bc 100755
--- a/litex_boards/targets/icebreaker_bitsy.py
+++ b/litex_boards/targets/icebreaker_bitsy.py
@@ -30,10 +30,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -116,17 +112,17 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on iCEBreaker-bitsy", **kwargs)
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
-        self.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.spram = Up5kSPRAM(size=128 * KILOBYTE)
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 0*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
         )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 64*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 64 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
             )
 
@@ -145,7 +141,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py
index 0816b32..91e288c 100755
--- a/litex_boards/targets/jungle_electronics_fireant.py
+++ b/litex_boards/targets/jungle_electronics_fireant.py
@@ -25,9 +25,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -82,7 +79,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index 128eead..4d8bb04 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -25,9 +25,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -87,17 +84,17 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Fomu", **kwargs)
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
-        self.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.spram = Up5kSPRAM(size=128 * KILOBYTE)
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 0*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
         )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["psram"].origin + 64*kB,
-                size   = 64*kB,
+                origin = self.bus.regions["psram"].origin + 64 * KILOBYTE,
+                size   = 64 * KILOBYTE,
                 linker = True)
             )
 
@@ -117,7 +114,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
@@ -137,7 +134,7 @@ def flash(build_dir, build_name, bios_flash_offset):
     bios      = open(f"{build_dir}/software/bios/bios.bin", "rb")
     image     = open(f"{build_dir}/image.bin", "wb")
     # Copy bitstream at 0.
-    assert bios_flash_offset >= 128*kB
+    assert bios_flash_offset >= 128 * KILOBYTE
     for i in range(0, bios_flash_offset):
         b = bitstream.read(1)
         if not b:
@@ -145,7 +142,7 @@ def flash(build_dir, build_name, bios_flash_offset):
         else:
             image.write(b)
     # Copy bios at bios_flash_offset.
-    for i in range(0, 32*kB):
+    for i in range(0, 32 * KILOBYTE):
         b = bios.read(1)
         if not b:
             image.write(0xff.to_bytes(1, "big"))
diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
index 43eb5d7..b6b6a0e 100755
--- a/litex_boards/targets/lattice_crosslink_nx_evn.py
+++ b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -25,10 +25,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -86,11 +82,11 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
 
         # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
-        self.spram = NXLRAM(32, 64*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16*kB))
+        self.spram = NXLRAM(32, 64 * KILOBYTE)
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=16 * KILOBYTE))
 
-        self.main_ram = NXLRAM(32, 64*kB)
-        self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64*kB))
+        self.main_ram = NXLRAM(32, 64 * KILOBYTE)
+        self.bus.add_slave("main_ram", self.main_ram.bus, SoCRegion(origin=self.mem_map["main_ram"], size=64 * KILOBYTE))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py
index ff17a99..827a1e9 100755
--- a/litex_boards/targets/lattice_crosslink_nx_vip.py
+++ b/litex_boards/targets/lattice_crosslink_nx_vip.py
@@ -28,10 +28,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -82,13 +78,13 @@ class BaseSoC(SoCCore):
         # SRAM/HyperRAM ----------------------------------------------------------------------------
         if hyperram == "none":
             # 128KB LRAM (used as SRAM) ------------------------------------------------------------
-            size = 128*kB
+            size = 128 * KILOBYTE
             self.spram = NXLRAM(32, size)
             self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(origin=self.mem_map["sram"],
                 size=size))
         else:
             # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
-            size = 8*1024*kB
+            size = 8*1024 * KILOBYTE
             hr_pads = platform.request("hyperram", int(hyperram))
             self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"],
diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
index 67e298b..68be67b 100755
--- a/litex_boards/targets/lattice_ice40up5k_evn.py
+++ b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -23,10 +23,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -72,8 +68,8 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Lattice iCE40UP5k EVN breakout board", **kwargs)
 
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
-        self.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
+        self.spram = Up5kSPRAM(size=128 * KILOBYTE)
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
 
         # SPI Flash --------------------------------------------------------------------------------
         # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA
@@ -84,7 +80,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/machdyne_krote.py b/litex_boards/targets/machdyne_krote.py
index ce90c55..d9e908b 100755
--- a/litex_boards/targets/machdyne_krote.py
+++ b/litex_boards/targets/machdyne_krote.py
@@ -36,10 +36,6 @@ from litex.soc.cores.led import LedChaser
 
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-kB = 1024
-mB = 1024*kB
-
-
 # _CRG ---------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -77,7 +73,7 @@ class BaseSoC(SoCCore):
 
         # Disable Integrated ROM since too large for iCE40.
         kwargs["integrated_rom_size"]  = 0
-        kwargs["integrated_sram_size"]  = 4*kB
+        kwargs["integrated_sram_size"]  = 4 * KILOBYTE
 
         # Set CPU variant / reset address
         kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
@@ -98,7 +94,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.mem_map["spiflash"] + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
 
diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py
index 13fbc83..01cad51 100755
--- a/litex_boards/targets/micronova_mercury2.py
+++ b/litex_boards/targets/micronova_mercury2.py
@@ -23,9 +23,6 @@ from litex.soc.interconnect import wishbone
 
 from litex.soc.integration.soc import colorer
 
-kB = 1024
-mB = 1024*kB
-
 # _CRG ---------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py
index a983fb1..e532222 100755
--- a/litex_boards/targets/muselab_icesugar.py
+++ b/litex_boards/targets/muselab_icesugar.py
@@ -22,9 +22,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -75,8 +72,8 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Muselab iCESugar", **kwargs)
 
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
-        self.spram = Up5kSPRAM(size=64*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.spram = Up5kSPRAM(size=64 * KILOBYTE)
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * KILOBYTE))
 
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import W25Q64FV
@@ -86,7 +83,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py
index 55e93fd..b976b23 100755
--- a/litex_boards/targets/qwertyembedded_beaglewire.py
+++ b/litex_boards/targets/qwertyembedded_beaglewire.py
@@ -27,9 +27,6 @@ from litex.soc.cores.uart import UARTWishboneBridge
 from litedram.phy import GENSDRPHY
 from litedram.modules import MT48LC32M8
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -70,7 +67,7 @@ class BaseSoC(SoCCore):
 
         # Disable Integrated ROM since too large for iCE40.
         kwargs["integrated_rom_size"]  = 0
-        kwargs["integrated_sram_size"] = 2*kB
+        kwargs["integrated_sram_size"] = 2 * KILOBYTE
 
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
@@ -95,7 +92,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py
index 7e95fc3..a731bb4 100755
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@@ -21,9 +21,6 @@ from litex.soc.cores.video import *
 
 from litex.soc.cores.hyperbus import HyperRAM
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -109,7 +106,7 @@ class BaseSoC(SoCCore):
             # Add ROM linker region ----------------------------------------------------------------
             self.bus.add_region("rom", SoCRegion(
                 origin = self.bus.regions["spiflash"].origin,
-                size   = 32*kB,
+                size   = 32 * KILOBYTE,
                 linker = True)
             )
             self.cpu.set_reset_address(self.bus.regions["rom"].origin)
@@ -128,7 +125,7 @@ class BaseSoC(SoCCore):
             self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
             self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
             self.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
+            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE))
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:
diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py
index d154632..28d5f5a 100755
--- a/litex_boards/targets/sipeed_tang_nano_9k.py
+++ b/litex_boards/targets/sipeed_tang_nano_9k.py
@@ -22,9 +22,6 @@ from litex.soc.cores.video import *
 
 from litex.soc.cores.hyperbus import HyperRAM
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -84,7 +81,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 64*kB,
+            size   = 64 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
@@ -115,7 +112,7 @@ class BaseSoC(SoCCore):
                 os.system("mv hyperbus.py.txt hyperbus.py")
             from hyperbus import HyperRAM
             self.hyperram = HyperRAM(hyperram_pads)
-            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
+            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4 * MEGABYTE))
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:
diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py
index 1e13a24..6147750 100755
--- a/litex_boards/targets/tinyfpga_bx.py
+++ b/litex_boards/targets/tinyfpga_bx.py
@@ -19,9 +19,6 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-kB = 1024
-mB = 1024*kB
-
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
@@ -44,7 +41,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)
diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py
index 4dad98a..b7f013d 100755
--- a/litex_boards/targets/trenz_tec0117.py
+++ b/litex_boards/targets/trenz_tec0117.py
@@ -25,9 +25,6 @@ from litex.soc.cores.led import LedChaser
 from litedram.modules import MT48LC4M16  # FIXME: use EtronTech reference.
 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
-kB = 1024
-mB = 1024*kB
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -79,7 +76,7 @@ class BaseSoC(SoCCore):
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
             origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
-            size   = 32*kB,
+            size   = 32 * KILOBYTE,
             linker = True)
         )
         self.cpu.set_reset_address(self.bus.regions["rom"].origin)