From ee5638a96b61b01cfa09bfaf8b2f7e8b14339445 Mon Sep 17 00:00:00 2001
From: Hans Baier <hansfbaier@gmail.com>
Date: Sat, 6 Nov 2021 06:49:25 +0700
Subject: [PATCH] qmtech-boards: fix serial so that it gets replaced by
 daughterboard serial correctly

---
 litex_boards/platforms/qmtech_10cl006.py | 16 ++++++++--------
 litex_boards/platforms/qmtech_5cefa2.py  | 16 ++++++++--------
 litex_boards/platforms/qmtech_ep4ce15.py | 15 +++++++--------
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py
index 7f669ed..7a882df 100644
--- a/litex_boards/platforms/qmtech_10cl006.py
+++ b/litex_boards/platforms/qmtech_10cl006.py
@@ -18,13 +18,6 @@ _io = [
     ("key", 0, Pins("F3"),  IOStandard("3.3-V LVTTL")),
     ("key", 1, Pins("J6"),  IOStandard("3.3-V LVTTL")),
 
-    # Serial
-    ("serial", 0,
-        # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
-        Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
-        Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))  # GPIO_05 (JP1 Pin 8)
-    ),
-
     # SPIFlash (W25Q64)
     ("spiflash", 0,
         # clk
@@ -128,7 +121,14 @@ _connectors = [
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
-    core_resources = [ ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")) ]
+    core_resources = [
+        ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")),
+        ("serial", 0,
+            # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
+            Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
+            Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))  # GPIO_05 (JP1 Pin 8)
+        ),
+    ]
 
     def __init__(self, with_daughterboard=False):
         device = "10CL006YU256C8G"
diff --git a/litex_boards/platforms/qmtech_5cefa2.py b/litex_boards/platforms/qmtech_5cefa2.py
index d52953e..d886162 100644
--- a/litex_boards/platforms/qmtech_5cefa2.py
+++ b/litex_boards/platforms/qmtech_5cefa2.py
@@ -18,12 +18,6 @@ _io = [
     ("key", 0, Pins("AB13"),  IOStandard("3.3-V LVTTL")),
     ("key", 1, Pins("V18"),  IOStandard("3.3-V LVTTL")),
 
-    # Serial
-    ("serial", 0,
-        Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")),
-        Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL"))
-    ),
-
     # SPIFlash (MT25QL128ABA)
     ("spiflash", 0,
         # clk
@@ -127,7 +121,13 @@ _connectors = [
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
-    core_resources = [ ("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")) ]
+    core_resources = [
+        ("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")),
+        ("serial", 0,
+            Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")),
+            Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL"))
+        ),
+ ]
 
     def __init__(self, with_daughterboard=False):
         device = "5CEFA2F23C8"
@@ -145,7 +145,7 @@ class Platform(AlteraPlatform):
         AlteraPlatform.__init__(self, device, io, connectors)
 
         if with_daughterboard:
-            # an ethernet pin takes the config pin, so make it available
+            # ethernet takes the config pin, so make it available
             self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
 
         # Generate PLL clock in STA
diff --git a/litex_boards/platforms/qmtech_ep4ce15.py b/litex_boards/platforms/qmtech_ep4ce15.py
index 36d0c38..cb51234 100644
--- a/litex_boards/platforms/qmtech_ep4ce15.py
+++ b/litex_boards/platforms/qmtech_ep4ce15.py
@@ -19,13 +19,6 @@ _io = [
     ("key", 0, Pins("Y13"),  IOStandard("3.3-V LVTTL")),
     ("key", 1, Pins("W13"),  IOStandard("3.3-V LVTTL")),
 
-    # Serial
-    ("serial", 0,
-        # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
-        Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
-        Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))  # GPIO_05 (JP1 Pin 8)
-    ),
-
     # SPIFlash (W25Q64)
     ("spiflash", 0,
         # clk
@@ -129,7 +122,13 @@ _connectors = [
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
-    core_resources = [ ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")) ]
+    core_resources = [
+        ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
+        ("serial", 0,
+            Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
+            Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
+        ),
+    ]
 
     def __init__(self, with_daughterboard=False):
         device = "EP4CE15F23C8"