From 2fb734a0f2099cb3a72780d22b609a04bfe09c10 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Mon, 29 Nov 2021 11:45:13 +0100 Subject: [PATCH 1/2] sipeed_tang_nano*: adapt Gowin PLL changes in litex --- litex_boards/targets/sipeed_tang_nano.py | 2 +- litex_boards/targets/sipeed_tang_nano_4k.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py index 7804150..e9727c7 100755 --- a/litex_boards/targets/sipeed_tang_nano.py +++ b/litex_boards/targets/sipeed_tang_nano.py @@ -57,7 +57,7 @@ class _CRG(Module): rst_n = platform.request("user_btn", 0) # PLL. - self.submodules.pll = pll = GW1NPLL(device="GW1N-1") + self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk24, 24e6) pll.create_clkout(self.cd_sys, sys_clk_freq) diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index a3e6c1e..d892f5c 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -12,7 +12,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.soc.cores.clock.gowin_gw1nsr import GW1NSRPLL +from litex.soc.cores.clock.gowin_gw1n import GW1NPLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * @@ -40,7 +40,7 @@ class _CRG(Module): rst_n = platform.request("user_btn", 0) # PLL - self.submodules.pll = pll = GW1NSRPLL(device="GW1NSR-4C") + self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk27, 27e6) pll.create_clkout(self.cd_sys, sys_clk_freq) @@ -48,7 +48,7 @@ class _CRG(Module): # Video PLL if with_video_pll: - self.submodules.video_pll = video_pll = GW1NSRPLL(device="GW1NSR-4C") + self.submodules.video_pll = video_pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.comb += video_pll.reset.eq(~rst_n) video_pll.register_clkin(clk27, 27e6) self.clock_domains.cd_hdmi = ClockDomain() From 666ef9dad3cc330e6bce90c063f4e5d6f3c1e70e Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Mon, 29 Nov 2021 11:46:32 +0100 Subject: [PATCH 2/2] sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs --- litex_boards/targets/sipeed_tang_nano_4k.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index d892f5c..df31fa3 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -72,6 +72,9 @@ class BaseSoC(SoCCore): kwargs["integrated_rom_size"] = 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0 + kwargs["cpu_type"] = 'vexriscv' + kwargs["cpu_variant"] = 'minimal' + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Tang Nano 4K",