From efb13bc1189d1af39b8bd8e35d8f70f1e2b919d1 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Apr 2020 16:31:07 +0200
Subject: [PATCH] add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS
 working.

---
 litex_boards/platforms/ecpix5.py | 56 ++++++++++++++++++++
 litex_boards/targets/ecpix5.py   | 89 ++++++++++++++++++++++++++++++++
 2 files changed, 145 insertions(+)
 create mode 100644 litex_boards/platforms/ecpix5.py
 create mode 100755 litex_boards/targets/ecpix5.py

diff --git a/litex_boards/platforms/ecpix5.py b/litex_boards/platforms/ecpix5.py
new file mode 100644
index 0000000..10f6bbb
--- /dev/null
+++ b/litex_boards/platforms/ecpix5.py
@@ -0,0 +1,56 @@
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # clock / reset
+    ("clk100", 0, Pins("K23"), IOStandard("LVCMOS33")),
+    ("rst_n",  0, Pins("N5"),  IOStandard("LVCMOS33")),
+
+    # led
+    ("rgb_led", 0,
+        Subsignal("r", Pins("U21")),
+        Subsignal("g", Pins("W21")),
+        Subsignal("b", Pins("T24")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("rgb_led", 1,
+        Subsignal("r", Pins("T23")),
+        Subsignal("g", Pins("R21")),
+        Subsignal("b", Pins("T22")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("rgb_led", 2,
+        Subsignal("r", Pins("P21")),
+        Subsignal("g", Pins("R23")),
+        Subsignal("b", Pins("P22")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("rgb_led", 3,
+        Subsignal("r", Pins("K21")),
+        Subsignal("g", Pins("K24")),
+        Subsignal("b", Pins("M21")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    # serial
+    ("serial", 0,
+        Subsignal("rx", Pins("R26"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("R24"), IOStandard("LVCMOS33")),
+    ),
+]
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk100"
+    default_clk_period = 1e9/100e6
+
+    def __init__(self, **kwargs):
+        LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG554I", _io, _connectors, **kwargs)
diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py
new file mode 100755
index 0000000..5fe98e8
--- /dev/null
+++ b/litex_boards/targets/ecpix5.py
@@ -0,0 +1,89 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+import argparse
+import sys
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import ecpix5
+
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys    = ClockDomain()
+
+        # # #
+
+        # Clk / Rst
+        clk100 = platform.request("clk100")
+        rst_n  = platform.request("rst_n")
+        platform.add_period_constraint(clk100, 1e9/100e6)
+
+        # PLL
+        self.submodules.pll = pll = ECP5PLL()
+
+        pll.register_clkin(clk100, 100e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+        platform = ecpix5.Platform(toolchain="trellis")
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+# Load ---------------------------------------------------------------------------------------------
+
+def load():
+    import os
+    f = open("openocd.cfg", "w")
+    f.write(
+"""
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 0
+ftdi_layout_init 0x00e8 0x60eb
+reset_config none
+adapter_khz 25000
+jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
+""")
+    f.close()
+    os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_ecpix5/gateware/top.svf; exit\"")
+    exit()
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
+    builder_args(parser)
+    soc_core_args(parser)
+    trellis_args(parser)
+    parser.add_argument("--load", action="store_true", help="load bitstream")
+    args = parser.parse_args()
+
+    if args.load:
+        load()
+
+    soc     = BaseSoC(**soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(**trellis_argdict(args))
+
+if __name__ == "__main__":
+    main()