diff --git a/litex_boards/platforms/qmtech_daughterboard.py b/litex_boards/platforms/qmtech_daughterboard.py
index 7cc616a..d6a5655 100644
--- a/litex_boards/platforms/qmtech_daughterboard.py
+++ b/litex_boards/platforms/qmtech_daughterboard.py
@@ -39,7 +39,7 @@ class SevenSeg(Module, AutoCSR):
 
         self.comb += Case(hexa, cases)
 
-        timer = WaitTimer(int(period*sys_clk_freq/(2*n)))
+        timer = WaitTimer(period*sys_clk_freq/(2*n))
         self.submodules += timer
         self.comb += timer.wait.eq(~timer.done)
         self.sync += If(timer.done,
diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py
index d97528e..6a49b96 100755
--- a/litex_boards/targets/gsd_orangecrab.py
+++ b/litex_boards/targets/gsd_orangecrab.py
@@ -65,7 +65,7 @@ class _CRG(LiteXModule):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(int(48e6))
+        reset_timer = WaitTimer(48e6)
         reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
@@ -135,7 +135,7 @@ class _CRGSDRAM(LiteXModule):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(int(48e6))
+        reset_timer = WaitTimer(48e6)
         reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)