diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py
index 31b8175..a08aa6a 100755
--- a/litex_boards/targets/alinx_axu2cga.py
+++ b/litex_boards/targets/alinx_axu2cga.py
@@ -77,23 +77,12 @@ class BaseSoC(SoCCore):
         if kwargs.get("cpu_type", None) == "zynqmp":
             kwargs["integrated_sram_size"] = 0
             kwargs["with_uart"] = False
-            self.mem_map = {
-                "csr": 0x8000_0000, # Zynq GP0 default
-            }
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXU2CGA", **kwargs)
 
         # ZynqMP Integration ---------------------------------------------------------------------
         if kwargs.get("cpu_type", None) == "zynqmp":
             self.cpu.config.update(platform.psu_config)
 
-            # Connect AXI HPM0 LPD to the SoC
-            wb_lpd = wishbone.Interface()
-            self.submodules += axi.AXI2Wishbone(
-                axi          = self.cpu.add_axi_gp_master(2, 32),
-                wishbone     = wb_lpd,
-                base_address = self.mem_map["csr"])
-            self.bus.add_master(master=wb_lpd)
-
             self.bus.add_region("sram", SoCRegion(
                 origin = self.cpu.mem_map["sram"],
                 size   = 1 * 1024 * 1024 * 1024)  # DDR
diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py
index 4eec0b7..c46c512 100755
--- a/litex_boards/targets/xilinx_kv260.py
+++ b/litex_boards/targets/xilinx_kv260.py
@@ -56,8 +56,6 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {"csr": 0xA000_0000}  # default GP0 address on ZynqMP
-
     def __init__(self, sys_clk_freq=100e6, **kwargs):
         platform = xilinx_kv260.Platform()
 
@@ -127,13 +125,6 @@ class BaseSoC(SoCCore):
                 'PSU__UART1__PERIPHERAL__IO'       : 'MIO 36 .. 37',
             })
 
-            # Connect Zynq AXI master to the SoC
-            wb_gp0 = wishbone.Interface()
-            self.submodules += axi.AXI2Wishbone(
-                axi          = self.cpu.add_axi_gp_master(),
-                wishbone     = wb_gp0,
-                base_address = self.mem_map["csr"])
-            self.bus.add_master(master=wb_gp0)
             self.bus.add_region("sram", SoCRegion(
                 origin = self.cpu.mem_map["sram"],
                 size   = 2 * 1024 * 1024 * 1024)  # DDR
diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py
index d656ca0..a2b4b12 100755
--- a/litex_boards/targets/xilinx_zcu216.py
+++ b/litex_boards/targets/xilinx_zcu216.py
@@ -46,8 +46,6 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {"csr": 0xA000_0000}  # default GP0 address on ZynqMP
-
     def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = xilinx_zcu216.Platform()
 
@@ -108,13 +106,6 @@ class BaseSoC(SoCCore):
                 'PSU__UART0__PERIPHERAL__IO'       : 'MIO 18 .. 19',
             })
 
-            # Connect Zynq AXI master to the SoC
-            wb_gp0 = wishbone.Interface()
-            self.submodules += axi.AXI2Wishbone(
-                axi          = self.cpu.add_axi_gp_master(),
-                wishbone     = wb_gp0,
-                base_address = self.mem_map["csr"])
-            self.bus.add_master(master=wb_gp0)
             self.bus.add_region("sram", SoCRegion(
                 origin = self.cpu.mem_map["sram"],
                 size   = 2 * 1024 * 1024 * 1024)  # DDR