From f080764c88e71f9e604802b8ab22741273df4102 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Jul 2021 12:03:37 +0200 Subject: [PATCH] test_targets: Collect platforms automatically. --- test/test_targets.py | 117 ++++--------------------------------------- 1 file changed, 10 insertions(+), 107 deletions(-) diff --git a/test/test_targets.py b/test/test_targets.py index 40e7274..77366e7 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -1,7 +1,7 @@ # # This file is part of LiteX-Boards. # -# This file is Copyright (c) 2017-2020 Florent Kermarrec +# This file is Copyright (c) 2017-2021 Florent Kermarrec # This file is Copyright (c) 2019 Tim 'mithro' Ansell # SPDX-License-Identifier: BSD-2-Clause @@ -25,118 +25,21 @@ def build_test(socs): class TestTargets(unittest.TestCase): - # Build simple design for all platforms + # Build simple design for all platforms. def test_simple(self): + # Collect platforms. platforms = [] + for file in os.listdir("./litex_boards/platforms/"): + if file.endswith(".py"): + file = file.replace(".py", "") + if file not in ["__init__", "qmtech_daughterboard"]: + platforms.append(file) - # Xilinx Spartan6 - platforms.append("linsn_rv901t") - platforms.append("minispartan6") - platforms.append("pipistrello") - platforms.append("sp605") - platforms.append("pano_logic_g2") - - # Xilinx Spartan7 - platforms.append("arty_s7") - - # Xilinx Artix7 - platforms.append("ac701") - platforms.append("aller") - platforms.append("arty") - platforms.append("basys3") - platforms.append("mimas_a7") - platforms.append("netv2") - platforms.append("nexys4ddr") - platforms.append("nexys_video") - platforms.append("tagus") - platforms.append("acorn") - platforms.append("marblemini") - platforms.append("qmtech_wukong") - platforms.append("qmtech_xc7a35t") - - # Xilinx Kintex7 - platforms.append("genesys2") - platforms.append("kc705") - platforms.append("mercury_kx2") - platforms.append("nereid") - - # Xilinx Virtex7 - platforms.append("vc707") - - # Xilinx Kintex Ultrascale - platforms.append("kcu105") - - # Xilinx Zynq-7000 - platforms.append("zedboard") - platforms.append("zybo_z7") - - # Xilinx Zynq Ultrascale+ - platforms.append("zcu104") - platforms.append("mercury_xu5") - - # Xilinx Virtex Ultrascale+ - platforms.append("vcu118") - - # Intel Cyclone3 - platforms.append("mist") - - # Intel Cyclone4 - platforms.append("de0nano") - platforms.append("de2_115") - platforms.append("qmtech_ep4ce15") - - # Intel Cyclone5 - platforms.append("de1soc") - platforms.append("de10nano") - platforms.append("sockit") - - # Intel Cyclone10 - platforms.append("c10lprefkit") - platforms.append("cyc1000") - - # Intel Max10 - platforms.append("de10lite") - platforms.append("deca") - - # Lattice iCE40 - platforms.append("fomu_evt") - platforms.append("fomu_hacker") - platforms.append("fomu_pvt") - platforms.append("tinyfpga_bx") - platforms.append("icebreaker") - platforms.append("icesugar") - - # Lattice MachXO2 - platforms.append("machxo3") - - # Lattice ECP5 - platforms.append("ecp5_evn") - platforms.append("hadbadge") - platforms.append("orangecrab") - platforms.append("trellisboard") - platforms.append("ulx3s") - platforms.append("versa_ecp5") - platforms.append("colorlight_5a_75b") - platforms.append("colorlight_5a_75e") - platforms.append("camlink_4k") - - # Lattice Crosslink NX - platforms.append("crosslink_nx_evn") - platforms.append("crosslink_nx_vip") - - # Gowin - platforms.append("tec0117") - - # Microsemi PolarFire - platforms.append("avalanche") - - # LPDDR4 Test Board - platforms.append("lpddr4_test_board") - + # Test platforms with simple design. for name in platforms: with self.subTest(platform=name): cmd = """\ -litex_boards/targets/simple.py litex_boards.platforms.{} \ +python3 -m litex_boards.targets.simple litex_boards.platforms.{} \ --no-compile-software \ --no-compile-gateware \ --uart-name="stub" \