diff --git a/litex_boards/platforms/muselab_icesugar_pro.py b/litex_boards/platforms/muselab_icesugar_pro.py
index 11ba868..cdaa2fd 100644
--- a/litex_boards/platforms/muselab_icesugar_pro.py
+++ b/litex_boards/platforms/muselab_icesugar_pro.py
@@ -89,13 +89,13 @@ _io = [
     # GPDI
     ("gpdi", 0,
         Subsignal("clk_p",   Pins("E2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
-        # Subsignal("clk_n",   Pins("D3"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
+        Subsignal("clk_n",   Pins("D3"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
         Subsignal("data0_p", Pins("G1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
-        # Subsignal("data0_n", Pins("F1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
+        Subsignal("data0_n", Pins("F1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
         Subsignal("data1_p", Pins("J1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
-        # Subsignal("data1_n", Pins("H2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
+        Subsignal("data1_n", Pins("H2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
         Subsignal("data2_p", Pins("L1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
-        # Subsignal("data2_n", Pins("K2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
+        Subsignal("data2_n", Pins("K2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
     ),
 ]
 
diff --git a/litex_boards/targets/muselab_icesugar_pro.py b/litex_boards/targets/muselab_icesugar_pro.py
index ec1ef9d..4c047fa 100755
--- a/litex_boards/targets/muselab_icesugar_pro.py
+++ b/litex_boards/targets/muselab_icesugar_pro.py
@@ -74,8 +74,8 @@ class _CRG(Module):
             video_pll.register_clkin(clk, clk_freq)
             self.clock_domains.cd_hdmi   = ClockDomain()
             self.clock_domains.cd_hdmi5x = ClockDomain()
-            video_pll.create_clkout(self.cd_hdmi,    40e6, margin=0)
-            video_pll.create_clkout(self.cd_hdmi5x, 200e6, margin=0)
+            video_pll.create_clkout(self.cd_hdmi,    25e6, margin=0)
+            video_pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
 
         # SDRAM clock
         sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
@@ -84,7 +84,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=60e6, with_led_chaser=True, with_spi_flash=False,
+    def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, with_spi_flash=False,
                  use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
                  with_video_framebuffer=False, **kwargs):
         platform = muselab_icesugar_pro.Platform()
@@ -121,9 +121,9 @@ class BaseSoC(SoCCore):
         if with_video_terminal or with_video_framebuffer:
             self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
             if with_video_terminal:
-                self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
+                self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
             if with_video_framebuffer:
-                self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
+                self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -133,7 +133,7 @@ def main():
     target_group = parser.add_argument_group(title="Target options")
     target_group.add_argument("--build",            action="store_true",      help="Build design.")
     target_group.add_argument("--load",             action="store_true",      help="Load bitstream.")
-    target_group.add_argument("--sys-clk-freq",     default=60e6,             help="System clock frequency.")
+    target_group.add_argument("--sys-clk-freq",     default=50e6,             help="System clock frequency.")
     sdopts = target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard",  action="store_true",  help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",      action="store_true",  help="Enable SDCard support.")
diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py
index 93ab49c..8de9979 100755
--- a/litex_boards/targets/sqrl_acorn.py
+++ b/litex_boards/targets/sqrl_acorn.py
@@ -104,10 +104,10 @@ class BaseSoC(SoCCore):
 
         # PCIe -------------------------------------------------------------------------------------
         if with_pcie:
-            self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
+            self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                 data_width = 128,
                 bar0_size  = 0x20000)
-            self.add_pcie(phy=self.pcie_phy, ndmas=1)
+            self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
             # FIXME: Apply it to all targets (integrate it in LitePCIe?).
             platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
             platform.toolchain.pre_placement_commands.add("set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks userclk2] -asynchronous", sys_clk=self.crg.cd_sys.clk)