diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py
index 76260bc..e7d07ce 100755
--- a/litex_boards/platforms/pano_logic_g2.py
+++ b/litex_boards/platforms/pano_logic_g2.py
@@ -9,6 +9,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -33,7 +34,7 @@ _io = [
     ),
 
     # serial
-    ("serial", 0, # dvi
+    ("serial", 1, # dvi
         Subsignal("tx", Pins("C14")),
         Subsignal("rx", Pins("C17")),
         IOStandard("LVCMOS33")
@@ -109,7 +110,12 @@ class Platform(XilinxPlatform):
     default_clk_name   = "clk125"
     default_clk_period = 1e9/125e6
 
-    def __init__(self, programmer="impact", device="xc6slx150"):
-        XilinxPlatform.__init__(self, "xc6slx150-2-fgg484", _io)
+    def __init__(self, revision="c"):
+        assert revision in ["b", "c"]
+        device = {"b": "xc6slx150-2-fgg484", "c": "xc6slx100-2-fgg484"}[revision]
+        XilinxPlatform.__init__(self, device, _io)
         self.add_platform_command("""CONFIG VCCAUX="2.5";""")
         self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
+
+    def create_programmer(self):
+        return OpenOCD("openocd_xc6_ft232.cfg")
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index d067ea1..7e1985f 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -35,8 +35,8 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), **kwargs):
-        platform = pano_logic_g2.Platform()
+    def __init__(self, revision, sys_clk_freq=int(50e6), **kwargs):
+        platform = pano_logic_g2.Platform(revision=revision)
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
@@ -54,13 +54,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",    action="store_true", help="Build bitstream")
+    parser.add_argument("--load",     action="store_true", help="Load bitstream")
+    parser.add_argument("--revision", default="c",         help="Board revision c (default) or b")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_core_argdict(args))
+    soc = BaseSoC(revision=args.revision, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)