From f1e24046fdb2aa64e7c2ea1fc6bb73a4248ef570 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 6 Nov 2022 22:16:11 +0100 Subject: [PATCH] xilinx_alveo_u250: Fix. --- litex_boards/targets/xilinx_alveo_u250.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index 1ca84ac..8e0a004 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -102,7 +102,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_alveo_u250.Platform, description="LiteX SoC on Alveo U250") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")