diff --git a/litex_boards/platforms/hpcstore_xc7k420t.py b/litex_boards/platforms/hpcstore_xc7k420t.py index f90e101..4b1970a 100644 --- a/litex_boards/platforms/hpcstore_xc7k420t.py +++ b/litex_boards/platforms/hpcstore_xc7k420t.py @@ -13,196 +13,202 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- -_io = [ - # Clk / Rst - ("clk100", 0, Pins("U24"), IOStandard("LVCMOS33")), - ("diffclk100", 0, - Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), - Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) - ), +def _get_io(io_standard): + _io = [ + # Clk / Rst + ("clk100", 0, Pins("U24"), io_standard), - # Leds - ("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")), - ("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")), - ("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")), - ("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")), - ("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")), - ("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")), - ("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")), - ("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")), + ("diffclk100", 0, + Subsignal("p", Pins("U22"), IOStandard("LVDS_25")), + Subsignal("n", Pins("U23"), IOStandard("LVDS_25")) + ), - # Buttons - ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), - ("user_btn_n", 1, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V + # Leds + ("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")), + ("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")), + ("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")), + ("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")), + ("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")), + ("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")), + ("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")), + ("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")), - # I2C / AT24C04 - ("i2c", 0, - Subsignal("scl", Pins("C17")), - Subsignal("sda", Pins("C16")), - IOStandard("LVCMOS33") - ), + # Buttons + ("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")), + ("cpu_reset_n", 0, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V - # Serial - ("serial", 0, - Subsignal("tx", Pins("D16")), # CH340_TX - Subsignal("rx", Pins("D17")), # CH340_RX - IOStandard("LVCMOS33") - ), + # I2C / AT24C04 + ("i2c", 0, + Subsignal("scl", Pins("C17")), + Subsignal("sda", Pins("C16")), + IOStandard("LVCMOS33") + ), - # DDR3 SDRAM near SFP ports - ("ddram", 0, - Subsignal("a", Pins( - "F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")), - Subsignal("dm", Pins( - "B22 E19 F22 K19 M23 P18 P26 N29"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21" + \ - "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23" + \ - "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19" + \ - "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), - Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), - Misc("SLEW=FAST"), - Misc("VCCAUX_IO=NORMAL") - ), + # Serial + ("serial", 0, + Subsignal("tx", Pins("D16")), # CH340_TX + Subsignal("rx", Pins("D17")), # CH340_RX + IOStandard("LVCMOS33") + ), - # DDR3 SDRAM near power supply - ("ddram", 1, - Subsignal("a", Pins( - "AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")), - Subsignal("dm", Pins( - "AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26" + \ - "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27" + \ - "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16" + \ - "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AH24"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), - Misc("SLEW=FAST"), - Misc("VCCAUX_IO=NORMAL") - ), + # DDR3 SDRAM near SFP ports + ("ddram", 0, + Subsignal("a", Pins( + "F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "B22 E19 F22 K19 M23 P18 P26 N29"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21 " + \ + "G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23 " + \ + "N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19 " + \ + "K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28 "), + IOStandard("SSTL15")), + Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("G25"), IOStandard("SSTL15")), + Subsignal("odt", Pins("J28"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + ), - # Sata - ("sata", 0, - Subsignal("rx_p", Pins("C12")), - Subsignal("rx_n", Pins("C11")), - Subsignal("tx_p", Pins("A12")), - Subsignal("tx_n", Pins("A11")), - IOStandard("LVDS"), - ), - ("sata", 1, - Subsignal("rx_p", Pins("E12")), - Subsignal("rx_n", Pins("E11")), - Subsignal("tx_p", Pins("B10")), - Subsignal("tx_n", Pins("B9")), - IOStandard("LVDS"), - ), + # DDR3 SDRAM near power supply + ("ddram", 1, + Subsignal("a", Pins( + "AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26 " + \ + "AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27 " + \ + "AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16 " + \ + "AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14 "), + IOStandard("SSTL15")), + Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AG20"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + ), - # PCIe - ("pcie_x1", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6")), - Subsignal("rx_n", Pins("P5")), - Subsignal("tx_p", Pins("N4")), - Subsignal("tx_n", Pins("N3")) - ), - ("pcie_x2", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("")), - Subsignal("rx_p", Pins("P6 R4")), - Subsignal("rx_n", Pins("P5 R3")), - Subsignal("tx_p", Pins("N4 P2")), - Subsignal("tx_n", Pins("N3 P1")) - ), - ("pcie_x4", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6 R4 U4 V6")), - Subsignal("rx_n", Pins("P5 R3 U3 V5")), - Subsignal("tx_p", Pins("N4 P2 T2 V2")), - Subsignal("tx_n", Pins("N3 P1 T1 V1")) - ), - ("pcie_x8", 0, - Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS33")), - Subsignal("clk_p", Pins("T6")), - Subsignal("clk_n", Pins("T5")), - Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), - Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")), - Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")), - Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1")) - ), + # Sata + ("sata", 0, + Subsignal("rx_p", Pins("C12")), + Subsignal("rx_n", Pins("C11")), + Subsignal("tx_p", Pins("A12")), + Subsignal("tx_n", Pins("A11")), + IOStandard("LVDS"), + ), + ("sata", 1, + Subsignal("rx_p", Pins("E12")), + Subsignal("rx_n", Pins("E11")), + Subsignal("tx_p", Pins("B10")), + Subsignal("tx_n", Pins("B9")), + IOStandard("LVDS"), + ), + + # PCIe + ("pcie_x1", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6")), + Subsignal("rx_n", Pins("P5")), + Subsignal("tx_p", Pins("N4")), + Subsignal("tx_n", Pins("N3")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("")), + Subsignal("rx_p", Pins("P6 R4")), + Subsignal("rx_n", Pins("P5 R3")), + Subsignal("tx_p", Pins("N4 P2")), + Subsignal("tx_n", Pins("N3 P1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1")) + ), + ("pcie_x8", 0, + Subsignal("rst_n", Pins("W21"), io_standard), + Subsignal("clk_p", Pins("T6")), + Subsignal("clk_n", Pins("T5")), + Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")), + Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")), + Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")), + Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1")) + ), - # SFP - ("sfp_a", 0, # SFP A - Subsignal("txp", Pins("A8")), - Subsignal("txn", Pins("A7")), - Subsignal("rxp", Pins("D10")), - Subsignal("rxn", Pins("D9")), - Subsignal("sda", Pins("C15")), - Subsignal("scl", Pins("A15")), - ), - ("sfp_a_tx", 0, # SFP A - Subsignal("p", Pins("A8")), - Subsignal("n", Pins("A7")) - ), - ("sfp_a_rx", 0, # SFP A - Subsignal("p", Pins("D10")), - Subsignal("n", Pins("D9")) - ), - ("sfp_b", 0, # SFP B - Subsignal("txp", Pins("C8")), - Subsignal("txn", Pins("C7")), - Subsignal("rxp", Pins("F10")), - Subsignal("rxn", Pins("F9")), - Subsignal("sda", Pins("C14")), - Subsignal("scl", Pins("B14")), - ), - ("sfp_b_tx", 0, # SFP B - Subsignal("p", Pins("C8")), - Subsignal("n", Pins("C7")) - ), - ("sfp_b_rx", 0, # SFP B - Subsignal("p", Pins("F10")), - Subsignal("n", Pins("F9")) - ), -] + # SFP A + ("sfp_a", 0, + Subsignal("txp", Pins("A8")), + Subsignal("txn", Pins("A7")), + Subsignal("rxp", Pins("D10")), + Subsignal("rxn", Pins("D9")), + Subsignal("sda", Pins("C15"), io_standard), + Subsignal("scl", Pins("A15"), io_standard), + ), + ("sfp_a_tx", 0, + Subsignal("p", Pins("A8")), + Subsignal("n", Pins("A7")) + ), + ("sfp_a_rx", 0, + Subsignal("p", Pins("D10")), + Subsignal("n", Pins("D9")) + ), + ("sfp_a_tx_disable_n", 0, Pins("Y20"), io_standard), + + # SFP B + ("sfp_b", 0, + Subsignal("txp", Pins("C8")), + Subsignal("txn", Pins("C7")), + Subsignal("rxp", Pins("F10")), + Subsignal("rxn", Pins("F9")), + Subsignal("sda", Pins("C14"), io_standard), + Subsignal("scl", Pins("B14"), io_standard), + ), + ("sfp_b_tx", 0, + Subsignal("p", Pins("C8")), + Subsignal("n", Pins("C7")) + ), + ("sfp_b_rx", 0, + Subsignal("p", Pins("F10")), + Subsignal("n", Pins("F9")) + ), + ("sfp_b_tx_disable_n", 0, Pins("D14"), io_standard), + ] + + return _io # Connectors --------------------------------------------------------------------------------------- @@ -311,13 +317,15 @@ class Platform(XilinxPlatform): default_clk_name = "diffclk100" default_clk_period = 1e9/100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ISE") - self.add_platform_command(""" - set_property CONFIG_VOLTAGE 3.3 [current_design] - set_property CFGBVS VCCO [current_design] - """) + def __init__(self, io_voltage="3.3V"): + assert io_voltage in ["2.5V", "3.3V"], "io_voltage must be '2.5V' or '3.3V' acording to the board jumper" + io_standard = IOStandard("LVCMOS33") if io_voltage == "3.3V" else IOStandard("LVCMOS25") + _io = _get_io(io_standard) + + XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ise") self.toolchain.bitstream_commands = [ + "set_property CONFIG_VOLTAGE 3.3 [current_design]", + "set_property CFGBVS VCCO [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", "set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]", diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py index d99be11..2997589 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -17,7 +17,7 @@ import os from migen import * -from litex_boards.platforms import aliexpress_stlv7325 +from litex_boards.platforms import hpcstore_xc7k420t from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -25,7 +25,7 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.bitbang import I2CMaster -from litedram.modules import MT8JTF12864 +from litedram.modules import K4B1G0446F from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY @@ -36,9 +36,10 @@ from litepcie.software import generate_litepcie_software class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain() - self.clock_domains.cd_idelay = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain() + self.clock_domains.cd_sys4x_dqs = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -47,12 +48,13 @@ class _CRG(Module): rst_n = platform.request("cpu_reset_n") # PLL. - self.submodules.pll = pll = S7MMCM(speedgrade=-2) + self.submodules.pll = pll = S7PLL(speedgrade=-2) self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_idelay, 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) @@ -61,11 +63,12 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), + io_voltage="3.3V", with_led_chaser = True, with_pcie = False, with_sata = False, **kwargs): - platform = aliexpress_stlv7325.Platform() + platform = hpcstore_xc7k420t.Platform(io_voltage) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -75,14 +78,16 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + # we need to use A7DDRPHY instead of K7DDRPHY, because the 420T has no ODELAYE2 + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram", 0), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6 ) self.add_sdram("sdram", phy = self.ddrphy, - module = MT8JTF12864(sys_clk_freq, "1:4"), + module = K4B1G0446F(sys_clk_freq, "1:4", "800"), l2_cache_size = kwargs.get("l2_size", 8192), ) @@ -131,10 +136,10 @@ def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress HPC Store XC7K420T") target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") - ethopts = target_group.add_mutually_exclusive_group() + target_group.add_argument("--build", action="store_true", help="Build design.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") + target_group.add_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'") target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.") target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.") target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.") @@ -144,6 +149,7 @@ def main(): soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), + io_voltage = args.io_voltage, with_pcie = args.with_pcie, with_sata = args.with_sata, **soc_core_argdict(args)