diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py
index 99e8b07..7efef10 100755
--- a/litex_boards/targets/simple.py
+++ b/litex_boards/targets/simple.py
@@ -36,10 +36,13 @@ class BaseSoC(SoCCore):
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
         # Leds -------------------------------------------------------------------------------------
-        self.submodules.leds = LedChaser(
-            pads         = platform.request_all("user_led"),
-            sys_clk_freq = sys_clk_freq)
-        self.add_csr("leds")
+        try:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("leds")
+        except:
+            pass
 
 # Build --------------------------------------------------------------------------------------------