diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 99d04c6..395142e 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import adi_adrv2crr_fmc diff --git a/litex_boards/targets/adi_plutosdr.py b/litex_boards/targets/adi_plutosdr.py index b7f4de1..d7f819a 100755 --- a/litex_boards/targets/adi_plutosdr.py +++ b/litex_boards/targets/adi_plutosdr.py @@ -13,7 +13,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import adi_plutosdr diff --git a/litex_boards/targets/alchitry_au.py b/litex_boards/targets/alchitry_au.py index fb847b8..21c5191 100755 --- a/litex_boards/targets/alchitry_au.py +++ b/litex_boards/targets/alchitry_au.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import alchitry_au diff --git a/litex_boards/targets/alchitry_mojo.py b/litex_boards/targets/alchitry_mojo.py index d7a42c1..180d249 100755 --- a/litex_boards/targets/alchitry_mojo.py +++ b/litex_boards/targets/alchitry_mojo.py @@ -41,7 +41,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput from litex_boards.platforms import alchitry_mojo diff --git a/litex_boards/targets/aliexpress_xc7k420t.py b/litex_boards/targets/aliexpress_xc7k420t.py index e50d8ff..a3f2783 100755 --- a/litex_boards/targets/aliexpress_xc7k420t.py +++ b/litex_boards/targets/aliexpress_xc7k420t.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import aliexpress_xc7k420t diff --git a/litex_boards/targets/alinx_ax7010.py b/litex_boards/targets/alinx_ax7010.py index f9a2df4..d39522b 100755 --- a/litex_boards/targets/alinx_ax7010.py +++ b/litex_boards/targets/alinx_ax7010.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import alinx_ax7010 diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index 33feae9..31b8175 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -20,7 +20,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import alinx_axu2cga diff --git a/litex_boards/targets/antmicro_artix_dc_scm.py b/litex_boards/targets/antmicro_artix_dc_scm.py index 75980a0..7fb00af 100755 --- a/litex_boards/targets/antmicro_artix_dc_scm.py +++ b/litex_boards/targets/antmicro_artix_dc_scm.py @@ -12,7 +12,7 @@ import math from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import antmicro_artix_dc_scm diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index a546fe2..d1fb956 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -11,7 +11,7 @@ import json from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import antmicro_datacenter_ddr4_test_board diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index 8548907..e8142b2 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -7,7 +7,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import antmicro_lpddr4_test_board diff --git a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py index 1d783ba..b8509ec 100755 --- a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py +++ b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import antmicro_sdi_mipi_video_converter diff --git a/litex_boards/targets/arduino_mkrvidor4000.py b/litex_boards/targets/arduino_mkrvidor4000.py index dde92c8..bde45fe 100755 --- a/litex_boards/targets/arduino_mkrvidor4000.py +++ b/litex_boards/targets/arduino_mkrvidor4000.py @@ -10,7 +10,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import arduino_mkrvidor4000 diff --git a/litex_boards/targets/avnet_aesku40.py b/litex_boards/targets/avnet_aesku40.py index 79d356f..fca1ff7 100755 --- a/litex_boards/targets/avnet_aesku40.py +++ b/litex_boards/targets/avnet_aesku40.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import avnet_aesku40 diff --git a/litex_boards/targets/berkeleylab_marble.py b/litex_boards/targets/berkeleylab_marble.py index 4756fcc..0e82722 100755 --- a/litex_boards/targets/berkeleylab_marble.py +++ b/litex_boards/targets/berkeleylab_marble.py @@ -26,7 +26,7 @@ then test and benchmark the etherbone link: from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import berkeleylab_marble diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 519e76a..d835485 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import camlink_4k diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 2a8af9e..5119780 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -43,7 +43,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py index 33b3783..e0e3f10 100755 --- a/litex_boards/targets/colorlight_i5.py +++ b/litex_boards/targets/colorlight_i5.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py index dc8dd73..f23693b 100755 --- a/litex_boards/targets/decklink_intensity_pro_4k.py +++ b/litex_boards/targets/decklink_intensity_pro_4k.py @@ -12,7 +12,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import decklink_intensity_pro_4k diff --git a/litex_boards/targets/decklink_mini_4k.py b/litex_boards/targets/decklink_mini_4k.py index 632a697..f8bb6d9 100755 --- a/litex_boards/targets/decklink_mini_4k.py +++ b/litex_boards/targets/decklink_mini_4k.py @@ -14,7 +14,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import decklink_mini_4k diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index 06a7b76..f6ed9d9 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -17,7 +17,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import decklink_quad_hdmi_recorder diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 7cbd8bb..2c581f3 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -14,7 +14,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_arty diff --git a/litex_boards/targets/digilent_arty_s7.py b/litex_boards/targets/digilent_arty_s7.py index 8330aa2..16914a6 100755 --- a/litex_boards/targets/digilent_arty_s7.py +++ b/litex_boards/targets/digilent_arty_s7.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_arty_s7 diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index dd9d387..4c8ef16 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -28,7 +28,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_arty_z7 from litex.build import tools diff --git a/litex_boards/targets/digilent_atlys.py b/litex_boards/targets/digilent_atlys.py index b3d0e24..fce4d9a 100755 --- a/litex_boards/targets/digilent_atlys.py +++ b/litex_boards/targets/digilent_atlys.py @@ -15,7 +15,7 @@ from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_atlys diff --git a/litex_boards/targets/digilent_basys3.py b/litex_boards/targets/digilent_basys3.py index a522d14..ae5e1e7 100755 --- a/litex_boards/targets/digilent_basys3.py +++ b/litex_boards/targets/digilent_basys3.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_basys3 diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index f5eb6b8..291b22f 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py index f1f9adb..52b507d 100755 --- a/litex_boards/targets/digilent_genesys2.py +++ b/litex_boards/targets/digilent_genesys2.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_genesys2 diff --git a/litex_boards/targets/digilent_nexys4.py b/litex_boards/targets/digilent_nexys4.py index 1b54fac..e9acb35 100755 --- a/litex_boards/targets/digilent_nexys4.py +++ b/litex_boards/targets/digilent_nexys4.py @@ -10,7 +10,7 @@ import math from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/digilent_nexys4ddr.py b/litex_boards/targets/digilent_nexys4ddr.py index 157929d..29d9197 100755 --- a/litex_boards/targets/digilent_nexys4ddr.py +++ b/litex_boards/targets/digilent_nexys4ddr.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_nexys4ddr diff --git a/litex_boards/targets/digilent_nexys_video.py b/litex_boards/targets/digilent_nexys_video.py index f7ac02f..dc3dddc 100755 --- a/litex_boards/targets/digilent_nexys_video.py +++ b/litex_boards/targets/digilent_nexys_video.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_nexys_video diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index ad4d9f7..a822137 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_pynq_z1 diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 324d56d..206e56c 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_zedboard from litex.build.tools import write_to_file diff --git a/litex_boards/targets/ebaz4205.py b/litex_boards/targets/ebaz4205.py index 083ef14..65d3775 100755 --- a/litex_boards/targets/ebaz4205.py +++ b/litex_boards/targets/ebaz4205.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import ebaz4205 diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py index 868d53e..6a0e89d 100755 --- a/litex_boards/targets/efinix_t8f81_dev_kit.py +++ b/litex_boards/targets/efinix_t8f81_dev_kit.py @@ -12,7 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_t8f81_dev_kit diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index e4d280a..5e06616 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_titanium_ti60_f225_dev_kit diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index 5312552..78ca785 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 9065093..a742ea8 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_trion_t20_bga256_dev_kit diff --git a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py index 80126d2..6a82573 100755 --- a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_trion_t20_mipi_dev_kit diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py index a8f9cef..b67327f 100755 --- a/litex_boards/targets/efinix_xyloni_dev_kit.py +++ b/litex_boards/targets/efinix_xyloni_dev_kit.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import efinix_xyloni_dev_kit diff --git a/litex_boards/targets/ego1.py b/litex_boards/targets/ego1.py index fb8a554..d4e096d 100755 --- a/litex_boards/targets/ego1.py +++ b/litex_boards/targets/ego1.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import ego1 diff --git a/litex_boards/targets/enclustra_mercury_kx2.py b/litex_boards/targets/enclustra_mercury_kx2.py index 052553c..5466bc2 100755 --- a/litex_boards/targets/enclustra_mercury_kx2.py +++ b/litex_boards/targets/enclustra_mercury_kx2.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import enclustra_mercury_kx2 diff --git a/litex_boards/targets/enclustra_mercury_xu5.py b/litex_boards/targets/enclustra_mercury_xu5.py index 6786fcd..71adff3 100755 --- a/litex_boards/targets/enclustra_mercury_xu5.py +++ b/litex_boards/targets/enclustra_mercury_xu5.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import enclustra_mercury_xu5 diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py index fc204a3..a443d1a 100755 --- a/litex_boards/targets/fairwaves_xtrx.py +++ b/litex_boards/targets/fairwaves_xtrx.py @@ -27,7 +27,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import fairwaves_xtrx diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index f547fcb..cb1868f 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import fpc_iii diff --git a/litex_boards/targets/fpgawars_alhambra2.py b/litex_boards/targets/fpgawars_alhambra2.py index e9cb70a..40d8a20 100755 --- a/litex_boards/targets/fpgawars_alhambra2.py +++ b/litex_boards/targets/fpgawars_alhambra2.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import fpgawars_alhambra2 diff --git a/litex_boards/targets/gadgetfactory_papilio_pro.py b/litex_boards/targets/gadgetfactory_papilio_pro.py index 00d88e7..2f53db6 100755 --- a/litex_boards/targets/gadgetfactory_papilio_pro.py +++ b/litex_boards/targets/gadgetfactory_papilio_pro.py @@ -10,7 +10,7 @@ import argparse from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index 7ed4f5d..02cf4d9 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -15,7 +15,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import gsd_butterstick diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index 74527cf..39fca73 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -13,7 +13,7 @@ from migen import * from migen.genlib.misc import WaitTimer from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import gsd_orangecrab diff --git a/litex_boards/targets/hackaday_hadbadge.py b/litex_boards/targets/hackaday_hadbadge.py index 1ab2d1f..261eeab 100755 --- a/litex_boards/targets/hackaday_hadbadge.py +++ b/litex_boards/targets/hackaday_hadbadge.py @@ -12,7 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/ice_v_wireless.py b/litex_boards/targets/ice_v_wireless.py index 4bad9f3..9ae8e07 100755 --- a/litex_boards/targets/ice_v_wireless.py +++ b/litex_boards/targets/ice_v_wireless.py @@ -17,7 +17,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import ice_v_wireless diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index c13d871..f92003a 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -20,7 +20,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import icebreaker diff --git a/litex_boards/targets/icebreaker_bitsy.py b/litex_boards/targets/icebreaker_bitsy.py index bb65e42..27534bd 100755 --- a/litex_boards/targets/icebreaker_bitsy.py +++ b/litex_boards/targets/icebreaker_bitsy.py @@ -19,7 +19,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import icebreaker_bitsy diff --git a/litex_boards/targets/isx_im1283.py b/litex_boards/targets/isx_im1283.py index 5cdbc35..bf4775e 100755 --- a/litex_boards/targets/isx_im1283.py +++ b/litex_boards/targets/isx_im1283.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import isx_im1283 diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py index 80b8a67..1a95632 100755 --- a/litex_boards/targets/jungle_electronics_fireant.py +++ b/litex_boards/targets/jungle_electronics_fireant.py @@ -12,7 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import jungle_electronics_fireant diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index e76be9f..128eead 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -14,7 +14,7 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import kosagi_fomu_pvt diff --git a/litex_boards/targets/kosagi_netv2.py b/litex_boards/targets/kosagi_netv2.py index c547820..55d83c7 100755 --- a/litex_boards/targets/kosagi_netv2.py +++ b/litex_boards/targets/kosagi_netv2.py @@ -10,7 +10,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import kosagi_netv2 diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index 3f11cd2..c78202c 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import krtkl_snickerdoodle diff --git a/litex_boards/targets/lambdaconcept_ecpix5.py b/litex_boards/targets/lambdaconcept_ecpix5.py index 5ccea40..3f78da4 100755 --- a/litex_boards/targets/lambdaconcept_ecpix5.py +++ b/litex_boards/targets/lambdaconcept_ecpix5.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lambdaconcept_ecpix5 diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index fb080fc..b5d822b 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_crosslink_nx_evn diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 7ffee5e..ff17a99 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -12,7 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_crosslink_nx_vip diff --git a/litex_boards/targets/lattice_ecp5_evn.py b/litex_boards/targets/lattice_ecp5_evn.py index d915f5e..304e137 100755 --- a/litex_boards/targets/lattice_ecp5_evn.py +++ b/litex_boards/targets/lattice_ecp5_evn.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_ecp5_evn diff --git a/litex_boards/targets/lattice_ecp5_vip.py b/litex_boards/targets/lattice_ecp5_vip.py index 8f0d311..1eb458e 100755 --- a/litex_boards/targets/lattice_ecp5_vip.py +++ b/litex_boards/targets/lattice_ecp5_vip.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_ecp5_vip diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py index 752e74a..685532d 100755 --- a/litex_boards/targets/lattice_ice40up5k_evn.py +++ b/litex_boards/targets/lattice_ice40up5k_evn.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_ice40up5k_evn from litex.build.lattice.programmer import IceStormProgrammer diff --git a/litex_boards/targets/lattice_versa_ecp5.py b/litex_boards/targets/lattice_versa_ecp5.py index 5bfa82c..495c775 100755 --- a/litex_boards/targets/lattice_versa_ecp5.py +++ b/litex_boards/targets/lattice_versa_ecp5.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import lattice_versa_ecp5 diff --git a/litex_boards/targets/limesdr_mini_v2.py b/litex_boards/targets/limesdr_mini_v2.py index 0d97ae4..1e35774 100755 --- a/litex_boards/targets/limesdr_mini_v2.py +++ b/litex_boards/targets/limesdr_mini_v2.py @@ -13,7 +13,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import limesdr_mini_v2 diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index e676698..66802ff 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/litex_acorn_baseboard.py b/litex_boards/targets/litex_acorn_baseboard.py index 7e61ecf..a42504a 100755 --- a/litex_boards/targets/litex_acorn_baseboard.py +++ b/litex_boards/targets/litex_acorn_baseboard.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import litex_acorn_baseboard diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 9d430ab..38af358 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -12,7 +12,7 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import logicbone diff --git a/litex_boards/targets/machdyne_krote.py b/litex_boards/targets/machdyne_krote.py index e116c07..ce90c55 100755 --- a/litex_boards/targets/machdyne_krote.py +++ b/litex_boards/targets/machdyne_krote.py @@ -22,7 +22,7 @@ import sys from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/machdyne_schoko.py b/litex_boards/targets/machdyne_schoko.py index f9fb6fe..c80fd56 100755 --- a/litex_boards/targets/machdyne_schoko.py +++ b/litex_boards/targets/machdyne_schoko.py @@ -14,7 +14,7 @@ import json from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import machdyne_schoko diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py index 8c2ebf7..13fbc83 100755 --- a/litex_boards/targets/micronova_mercury2.py +++ b/litex_boards/targets/micronova_mercury2.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index b985caf..a7499db 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py index 0c50e57..a7e7867 100755 --- a/litex_boards/targets/mnt_rkx7.py +++ b/litex_boards/targets/mnt_rkx7.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import mnt_rkx7 diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py index 65a3c9c..a983fb1 100755 --- a/litex_boards/targets/muselab_icesugar.py +++ b/litex_boards/targets/muselab_icesugar.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import muselab_icesugar diff --git a/litex_boards/targets/muselab_icesugar_pro.py b/litex_boards/targets/muselab_icesugar_pro.py index df9fdd8..027b733 100755 --- a/litex_boards/targets/muselab_icesugar_pro.py +++ b/litex_boards/targets/muselab_icesugar_pro.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/myminieye_runber.py b/litex_boards/targets/myminieye_runber.py index 9021333..93b23f0 100755 --- a/litex_boards/targets/myminieye_runber.py +++ b/litex_boards/targets/myminieye_runber.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * diff --git a/litex_boards/targets/newae_cw305.py b/litex_boards/targets/newae_cw305.py index 22a92ba..78d403e 100755 --- a/litex_boards/targets/newae_cw305.py +++ b/litex_boards/targets/newae_cw305.py @@ -13,7 +13,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import newae_cw305 diff --git a/litex_boards/targets/numato_aller.py b/litex_boards/targets/numato_aller.py index d8b3fb7..058e3d0 100755 --- a/litex_boards/targets/numato_aller.py +++ b/litex_boards/targets/numato_aller.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import numato_aller diff --git a/litex_boards/targets/numato_mimas_a7.py b/litex_boards/targets/numato_mimas_a7.py index d907272..6e859cd 100755 --- a/litex_boards/targets/numato_mimas_a7.py +++ b/litex_boards/targets/numato_mimas_a7.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import numato_mimas_a7 diff --git a/litex_boards/targets/numato_nereid.py b/litex_boards/targets/numato_nereid.py index e9dda94..9a649a8 100755 --- a/litex_boards/targets/numato_nereid.py +++ b/litex_boards/targets/numato_nereid.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import numato_nereid diff --git a/litex_boards/targets/numato_tagus.py b/litex_boards/targets/numato_tagus.py index 525fcd2..6db9eae 100755 --- a/litex_boards/targets/numato_tagus.py +++ b/litex_boards/targets/numato_tagus.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import numato_tagus diff --git a/litex_boards/targets/ocp_tap_timecard.py b/litex_boards/targets/ocp_tap_timecard.py index dcb8e4b..669193c 100755 --- a/litex_boards/targets/ocp_tap_timecard.py +++ b/litex_boards/targets/ocp_tap_timecard.py @@ -27,7 +27,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import ocp_tap_timecard diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 8abd613..18873da 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import pano_logic_g2 diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py index 187c515..f1d7bf5 100755 --- a/litex_boards/targets/qmtech_10cl006.py +++ b/litex_boards/targets/qmtech_10cl006.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/qmtech_5cefa2.py b/litex_boards/targets/qmtech_5cefa2.py index 76bb677..c0b4f65 100755 --- a/litex_boards/targets/qmtech_5cefa2.py +++ b/litex_boards/targets/qmtech_5cefa2.py @@ -10,7 +10,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py index 727edd7..5f36fcf 100755 --- a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py +++ b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/qmtech_ep4cex5.py b/litex_boards/targets/qmtech_ep4cex5.py index 0875f40..eeae1ce 100755 --- a/litex_boards/targets/qmtech_ep4cex5.py +++ b/litex_boards/targets/qmtech_ep4cex5.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/qmtech_ep4cgx150.py b/litex_boards/targets/qmtech_ep4cgx150.py index c7f75e2..b64c952 100755 --- a/litex_boards/targets/qmtech_ep4cgx150.py +++ b/litex_boards/targets/qmtech_ep4cgx150.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/qmtech_wukong.py b/litex_boards/targets/qmtech_wukong.py index 687250f..25c1fc2 100755 --- a/litex_boards/targets/qmtech_wukong.py +++ b/litex_boards/targets/qmtech_wukong.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import qmtech_wukong diff --git a/litex_boards/targets/qmtech_xc7a35t.py b/litex_boards/targets/qmtech_xc7a35t.py index fee27e8..5d41d36 100755 --- a/litex_boards/targets/qmtech_xc7a35t.py +++ b/litex_boards/targets/qmtech_xc7a35t.py @@ -10,7 +10,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import qmtech_xc7a35t diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index 48abf1e..3bbbae6 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import quicklogic_quickfeather diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index f8c233f..55e93fd 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import qwertyembedded_beaglewire diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py index fe8b8c1..15c1298 100755 --- a/litex_boards/targets/radiona_ulx3s.py +++ b/litex_boards/targets/radiona_ulx3s.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/radiona_ulx4m_ld_v2.py b/litex_boards/targets/radiona_ulx4m_ld_v2.py index 72ddc74..a93e9d4 100755 --- a/litex_boards/targets/radiona_ulx4m_ld_v2.py +++ b/litex_boards/targets/radiona_ulx4m_ld_v2.py @@ -17,7 +17,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import radiona_ulx4m_ld_v2 from litex.soc.cores.clock import * diff --git a/litex_boards/targets/rcs_arctic_tern_bmc_card.py b/litex_boards/targets/rcs_arctic_tern_bmc_card.py index 1665146..71f9830 100755 --- a/litex_boards/targets/rcs_arctic_tern_bmc_card.py +++ b/litex_boards/targets/rcs_arctic_tern_bmc_card.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import rcs_arctic_tern_bmc_card diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index 4804227..e4d560f 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -10,7 +10,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import redpitaya diff --git a/litex_boards/targets/rz_easyfpga.py b/litex_boards/targets/rz_easyfpga.py index 5a0a68c..0923a12 100755 --- a/litex_boards/targets/rz_easyfpga.py +++ b/litex_boards/targets/rz_easyfpga.py @@ -10,7 +10,7 @@ from migen import * from litex.build.io import DDROutput -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import rz_easyfpga diff --git a/litex_boards/targets/saanlima_pipistrello.py b/litex_boards/targets/saanlima_pipistrello.py index 19518fd..85dfbeb 100755 --- a/litex_boards/targets/saanlima_pipistrello.py +++ b/litex_boards/targets/saanlima_pipistrello.py @@ -15,7 +15,7 @@ from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import saanlima_pipistrello diff --git a/litex_boards/targets/scarabhardware_minispartan6.py b/litex_boards/targets/scarabhardware_minispartan6.py index 0e52c7b..952af6b 100755 --- a/litex_boards/targets/scarabhardware_minispartan6.py +++ b/litex_boards/targets/scarabhardware_minispartan6.py @@ -11,7 +11,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py index a41709b..18bccfb 100755 --- a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py +++ b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.generic_platform import * diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index 1779449..1268794 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -20,7 +20,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import siglent_sds1104xe diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 439464b..4eb7cce 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -11,7 +11,7 @@ import importlib from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py index 66bdb94..3960384 100755 --- a/litex_boards/targets/sipeed_tang_nano.py +++ b/litex_boards/targets/sipeed_tang_nano.py @@ -31,7 +31,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sipeed_tang_nano diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 7bd4a53..a14d060 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sipeed_tang_nano_4k diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py index ba06142..d154632 100755 --- a/litex_boards/targets/sipeed_tang_nano_9k.py +++ b/litex_boards/targets/sipeed_tang_nano_9k.py @@ -9,7 +9,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sipeed_tang_nano_9k diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py index 9f3827c..f6f79be 100755 --- a/litex_boards/targets/sipeed_tang_primer.py +++ b/litex_boards/targets/sipeed_tang_primer.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sipeed_tang_primer diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py index 32a4f5d..52ac54c 100755 --- a/litex_boards/targets/sipeed_tang_primer_20k.py +++ b/litex_boards/targets/sipeed_tang_primer_20k.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.soc.cores.clock.gowin_gw2a import GW2APLL from litex.soc.integration.soc_core import * diff --git a/litex_boards/targets/sitlinv_a_e115fb.py b/litex_boards/targets/sitlinv_a_e115fb.py index 1049db3..4883d42 100755 --- a/litex_boards/targets/sitlinv_a_e115fb.py +++ b/litex_boards/targets/sitlinv_a_e115fb.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sitlinv_a_e115fb diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index 83ff03b..c8e2650 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -13,7 +13,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sitlinv_stlv7325 diff --git a/litex_boards/targets/sitlinv_xc7k420t.py b/litex_boards/targets/sitlinv_xc7k420t.py index dc2d86f..9a0ee0b 100755 --- a/litex_boards/targets/sitlinv_xc7k420t.py +++ b/litex_boards/targets/sitlinv_xc7k420t.py @@ -17,7 +17,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sitlinv_xc7k420t diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index 1583b6e..8919d0d 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -27,7 +27,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sqrl_acorn diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py index bb7242a..9fac732 100755 --- a/litex_boards/targets/sqrl_fk33.py +++ b/litex_boards/targets/sqrl_fk33.py @@ -15,7 +15,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sqrl_fk33 diff --git a/litex_boards/targets/sqrl_xcu1525.py b/litex_boards/targets/sqrl_xcu1525.py index 819020a..a49d578 100755 --- a/litex_boards/targets/sqrl_xcu1525.py +++ b/litex_boards/targets/sqrl_xcu1525.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import sqrl_xcu1525 diff --git a/litex_boards/targets/terasic_de0nano.py b/litex_boards/targets/terasic_de0nano.py index 86e8483..f9fed36 100755 --- a/litex_boards/targets/terasic_de0nano.py +++ b/litex_boards/targets/terasic_de0nano.py @@ -13,7 +13,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/terasic_de10lite.py b/litex_boards/targets/terasic_de10lite.py index 7aec733..8123738 100755 --- a/litex_boards/targets/terasic_de10lite.py +++ b/litex_boards/targets/terasic_de10lite.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/terasic_de10nano.py b/litex_boards/targets/terasic_de10nano.py index 3956d59..2476877 100755 --- a/litex_boards/targets/terasic_de10nano.py +++ b/litex_boards/targets/terasic_de10nano.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/terasic_de1soc.py b/litex_boards/targets/terasic_de1soc.py index ab2d80c..36fe8b0 100755 --- a/litex_boards/targets/terasic_de1soc.py +++ b/litex_boards/targets/terasic_de1soc.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/terasic_de2_115.py b/litex_boards/targets/terasic_de2_115.py index 9715b47..42cc11e 100755 --- a/litex_boards/targets/terasic_de2_115.py +++ b/litex_boards/targets/terasic_de2_115.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import DDROutput diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py index 4be19a5..6dc261f 100755 --- a/litex_boards/targets/terasic_deca.py +++ b/litex_boards/targets/terasic_deca.py @@ -13,7 +13,7 @@ from migen import * from litex_boards.platforms import terasic_deca -from litex.gen import LiteXModule +from litex.gen import * from litex.soc.cores.clock import Max10PLL from litex.soc.integration.soc_core import * diff --git a/litex_boards/targets/terasic_sockit.py b/litex_boards/targets/terasic_sockit.py index 5c6b9f5..6685b9f 100755 --- a/litex_boards/targets/terasic_sockit.py +++ b/litex_boards/targets/terasic_sockit.py @@ -7,7 +7,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import terasic_sockit diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py index d07d933..1e13a24 100755 --- a/litex_boards/targets/tinyfpga_bx.py +++ b/litex_boards/targets/tinyfpga_bx.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex.build.io import CRG diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 170ae65..926aa2c 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trellisboard diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index 0d336dd..db5aff2 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -10,7 +10,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trenz_c10lprefkit diff --git a/litex_boards/targets/trenz_cyc1000.py b/litex_boards/targets/trenz_cyc1000.py index c87dede..954773b 100755 --- a/litex_boards/targets/trenz_cyc1000.py +++ b/litex_boards/targets/trenz_cyc1000.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trenz_cyc1000 diff --git a/litex_boards/targets/trenz_max1000.py b/litex_boards/targets/trenz_max1000.py index f44d383..973d070 100755 --- a/litex_boards/targets/trenz_max1000.py +++ b/litex_boards/targets/trenz_max1000.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trenz_max1000 diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py index 0b751d5..84d9656 100755 --- a/litex_boards/targets/trenz_te0725.py +++ b/litex_boards/targets/trenz_te0725.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trenz_te0725 diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index 1408956..4dad98a 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import trenz_tec0117 diff --git a/litex_boards/targets/tul_pynq_z2.py b/litex_boards/targets/tul_pynq_z2.py index 338ace9..5f08887 100755 --- a/litex_boards/targets/tul_pynq_z2.py +++ b/litex_boards/targets/tul_pynq_z2.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import tul_pynq_z2 diff --git a/litex_boards/targets/xilinx_ac701.py b/litex_boards/targets/xilinx_ac701.py index eb9822f..9205c2d 100755 --- a/litex_boards/targets/xilinx_ac701.py +++ b/litex_boards/targets/xilinx_ac701.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_ac701 diff --git a/litex_boards/targets/xilinx_alveo_u200.py b/litex_boards/targets/xilinx_alveo_u200.py index c6acb89..b817ce9 100755 --- a/litex_boards/targets/xilinx_alveo_u200.py +++ b/litex_boards/targets/xilinx_alveo_u200.py @@ -14,7 +14,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_alveo_u200 diff --git a/litex_boards/targets/xilinx_alveo_u250.py b/litex_boards/targets/xilinx_alveo_u250.py index 3128a96..247e32b 100755 --- a/litex_boards/targets/xilinx_alveo_u250.py +++ b/litex_boards/targets/xilinx_alveo_u250.py @@ -13,7 +13,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_alveo_u250 diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index fa655d3..0cf89e8 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -17,7 +17,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_alveo_u280 diff --git a/litex_boards/targets/xilinx_kc705.py b/litex_boards/targets/xilinx_kc705.py index c8046e2..03158bc 100755 --- a/litex_boards/targets/xilinx_kc705.py +++ b/litex_boards/targets/xilinx_kc705.py @@ -12,7 +12,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_kc705 diff --git a/litex_boards/targets/xilinx_kcu105.py b/litex_boards/targets/xilinx_kcu105.py index 9b789f8..9f1d6a2 100755 --- a/litex_boards/targets/xilinx_kcu105.py +++ b/litex_boards/targets/xilinx_kcu105.py @@ -11,7 +11,7 @@ import os from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_kcu105 diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index 87848c8..4eec0b7 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -20,7 +20,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_kv260 from litex.build.tools import write_to_file diff --git a/litex_boards/targets/xilinx_vc707.py b/litex_boards/targets/xilinx_vc707.py index 5127bf9..f6ecd43 100755 --- a/litex_boards/targets/xilinx_vc707.py +++ b/litex_boards/targets/xilinx_vc707.py @@ -9,7 +9,7 @@ import os from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_vc707 diff --git a/litex_boards/targets/xilinx_vcu118.py b/litex_boards/targets/xilinx_vcu118.py index 36cf9e8..a6f799f 100755 --- a/litex_boards/targets/xilinx_vcu118.py +++ b/litex_boards/targets/xilinx_vcu118.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_vcu118 diff --git a/litex_boards/targets/xilinx_zcu102.py b/litex_boards/targets/xilinx_zcu102.py index 8c9e5a1..9e98f99 100755 --- a/litex_boards/targets/xilinx_zcu102.py +++ b/litex_boards/targets/xilinx_zcu102.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_zcu102 diff --git a/litex_boards/targets/xilinx_zcu104.py b/litex_boards/targets/xilinx_zcu104.py index d38cb00..c01898a 100755 --- a/litex_boards/targets/xilinx_zcu104.py +++ b/litex_boards/targets/xilinx_zcu104.py @@ -10,7 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_zcu104 diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py index 48f0c41..ce80aa9 100755 --- a/litex_boards/targets/xilinx_zcu106.py +++ b/litex_boards/targets/xilinx_zcu106.py @@ -9,7 +9,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_zcu106 diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index b577f50..d656ca0 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -8,7 +8,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import xilinx_zcu216 diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index cbc9bcb..6425780 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -9,7 +9,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import digilent_zybo_z7 diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index b72c8e2..3a91de3 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -15,7 +15,7 @@ from migen import * -from litex.gen import LiteXModule +from litex.gen import * from litex_boards.platforms import ztex213