diff --git a/litex_boards/platforms/alinx_axau15.py b/litex_boards/platforms/alinx_axau15.py
index bf9de4f..2d61592 100644
--- a/litex_boards/platforms/alinx_axau15.py
+++ b/litex_boards/platforms/alinx_axau15.py
@@ -16,7 +16,7 @@ _io = [
         Subsignal("n", Pins("U24"), IOStandard("LVDS"))
     ),
 
-    ("clk156", 0,
+    ("clk156p25", 0,
         Subsignal("p", Pins("T7"), IOStandard("LVDS")),
         Subsignal("n", Pins("T6"), IOStandard("LVDS"))
     ),
@@ -26,7 +26,7 @@ _io = [
     ("user_btn", 1, Pins("AA23"), IOStandard("LVCMOS33")),
 
     # Leds.
-    ("user_led", 0, Pins("W21"), IOStandard("LVCMOS18")),
+    ("user_led", 0, Pins("W21"),  IOStandard("LVCMOS18")),
     ("user_led", 1, Pins("AC16"), IOStandard("LVCMOS18")),
 
     # Serial.
diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py
index 327141c..f3132a7 100755
--- a/litex_boards/targets/alinx_axau15.py
+++ b/litex_boards/targets/alinx_axau15.py
@@ -46,6 +46,8 @@ class _CRG(LiteXModule):
         pll.create_clkout(self.cd_sys,    sys_clk_freq, with_reset=False)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
+
+        # IDelayCtrl.
         self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_sys4x, cd_sys=self.cd_sys)
 
 # BaseSoC ------------------------------------------------------------------------------------------
@@ -64,15 +66,15 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        kwargs["uart_name"] = "serial"
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AXAU15", **kwargs)
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alinx AXAU15", **kwargs)
 
         # DDR4 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 500e6)
+                iodelay_clk_freq = 500e6
+            )
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
                 module        = MT40A512M16(sys_clk_freq, "1:4"),