diff --git a/litex_boards/targets/machdyne_konfekt.py b/litex_boards/targets/machdyne_konfekt.py
index 1f4476f..085af01 100755
--- a/litex_boards/targets/machdyne_konfekt.py
+++ b/litex_boards/targets/machdyne_konfekt.py
@@ -31,7 +31,6 @@ from litedram.modules import W9825G6KH6
 from litedram.modules import IS42S16320
 
 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
-from litedram.phy import QuarterRateGENSDRPHY
 
 from litex.soc.integration.soc import SoCRegion
 
@@ -120,6 +119,7 @@ class BaseSoC(SoCCore):
             if sdram_rate == "1:2":
                 sdrphy_cls = HalfRateGENSDRPHY
             elif sdram_rate == "1:4":
+                from litedram.phy import QuarterRateGENSDRPHY
                 sdrphy_cls = QuarterRateGENSDRPHY
             else:
                 sdrphy_cls = GENSDRPHY
diff --git a/litex_boards/targets/machdyne_noir.py b/litex_boards/targets/machdyne_noir.py
index dff1e93..e4c582d 100755
--- a/litex_boards/targets/machdyne_noir.py
+++ b/litex_boards/targets/machdyne_noir.py
@@ -33,9 +33,6 @@ from litex.soc.integration.builder import *
 from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
 from litedram.phy import ECP5DDRPHY
 
-from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
-from litedram.phy import QuarterRateGENSDRPHY
-
 from litex.soc.integration.soc import SoCRegion
 
 # CRG ---------------------------------------------------------------------------------------------