From 2264df8a0a92267b0050d500d27549eb5f3e3e0b Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Mon, 5 Feb 2024 11:42:14 +0100 Subject: [PATCH 1/2] adi_adrv2crr_fmc: Speedgrade of the PLL is -2 Speedgrade of the chip was updated in a previous commit, but I forgot to update the PLL too Signed-off-by: Sylvain Munaut --- litex_boards/targets/adi_adrv2crr_fmc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 5597c61..013cec0 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -41,7 +41,7 @@ class CRG(LiteXModule): # # # - self.pll = pll = USPMMCM(speedgrade=-1) + self.pll = pll = USPMMCM(speedgrade=-2) self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) From b3caabcca3c95fe5f6209c2df372554daa08998e Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Mon, 5 Feb 2024 11:43:02 +0100 Subject: [PATCH 2/2] di_adrv2crr_fmc: Bump PCIe to 8 lanes There used to be an issue with 8 lanes litepcie USP for that board when it was first added, but it's been solved now, so might as well use all the available lanes Signed-off-by: Sylvain Munaut --- litex_boards/targets/adi_adrv2crr_fmc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 013cec0..5b8f60f 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -93,9 +93,9 @@ class BaseSoC(SoCCore): if with_pcie: assert self.csr_data_width == 32 - self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), + self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x8"), speed = "gen3", - data_width = 128, + data_width = 256, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1)