Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #563 from smunaut/adi 

Some minor updates to the ADI ADRV2CRR board
This commit is contained in:
enjoy-digital 2024-02-06 16:33:53 +01:00 committed by GitHub
parent a6f8f0e696 b3caabcca3
commit f7c7a5a7e5
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex_boards/targets/adi_adrv2crr_fmc.py
View File

@ -41,7 +41,7 @@ class CRG(LiteXModule):
# # #
self.pll = pll = USPMMCM(speedgrade=-1)
self.pll = pll = USPMMCM(speedgrade=-2)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
@ -93,9 +93,9 @@ class BaseSoC(SoCCore):
if with_pcie:
assert self.csr_data_width == 32
self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x8"),
speed = "gen3",
data_width = 128,
data_width = 256,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)