From f7fbfb46399d52d34008202b77c7ba247e678e44 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 Dec 2019 09:33:08 +0100 Subject: [PATCH] partner/community/targets: uniformize, improve presentation --- litex_boards/community/targets/ac701.py | 44 +++++++++------ litex_boards/community/targets/de10lite.py | 55 ++++++++++--------- litex_boards/community/targets/de1soc.py | 52 ++++++++++-------- litex_boards/community/targets/de2_115.py | 56 ++++++++++--------- litex_boards/community/targets/ecp5_evn.py | 14 +++-- litex_boards/partner/targets/aller.py | 51 ++++++++--------- litex_boards/partner/targets/c10lprefkit.py | 58 +++++++++++--------- litex_boards/partner/targets/nereid.py | 47 ++++++++-------- litex_boards/partner/targets/tagus.py | 45 ++++++++------- litex_boards/partner/targets/trellisboard.py | 53 +++++++++--------- 10 files changed, 256 insertions(+), 219 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index 50b5cc3..16d521d 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -27,10 +27,10 @@ from liteeth.mac import LiteEthMAC class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() # # # @@ -41,10 +41,10 @@ class _CRG(Module): self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk200"), 200e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk200, 200e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) @@ -53,20 +53,27 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = ac701.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - integrated_sram_size=0x8000, - **kwargs) + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + integrated_sram_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - # sdram - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") - sdram_module = MT8JTF12864(sys_clk_freq, "1:4") - self.register_sdram(self.ddrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq) + self.add_csr("ddrphy") + sdram_module = MT8JTF12864(sys_clk_freq, "1:4") + self.register_sdram(self.ddrphy, + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # EthernetSoC -------------------------------------------------------------------------------------- @@ -80,6 +87,7 @@ class EthernetSoC(BaseSoC): assert phy in ["rgmii", "1000basex"] BaseSoC.__init__(self, **kwargs) + # RGMII Ethernet PHY ----------------------------------------------------------------------- if phy == "rgmii": self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) @@ -93,6 +101,7 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) + # 1000BaseX Ethernet PHY ------------------------------------------------------------------- if phy == "1000basex": self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) @@ -120,6 +129,7 @@ class EthernetSoC(BaseSoC): self.ethphy.txoutclk, self.ethphy.rxoutclk) + # Ethernet MAC ----------------------------------------------------------------------------- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py index eb7a5f1..468dc60 100755 --- a/litex_boards/community/targets/de10lite.py +++ b/litex_boards/community/targets/de10lite.py @@ -16,11 +16,12 @@ from litedram.modules import IS42S16320 from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- + class _CRG(Module): def __init__(self, platform): - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # @@ -42,24 +43,24 @@ class _CRG(Module): self.comb += self.cd_sys.clk.eq(clk50) self.specials += \ Instance("ALTPLL", - p_BANDWIDTH_TYPE="AUTO", - p_CLK0_DIVIDE_BY=1, - p_CLK0_DUTY_CYCLE=50, - p_CLK0_MULTIPLY_BY=1, - p_CLK0_PHASE_SHIFT="-10000", - p_COMPENSATE_CLOCK="CLK0", - p_INCLK0_INPUT_FREQUENCY=20000, - p_INTENDED_DEVICE_FAMILY="MAX 10", - p_LPM_TYPE = "altpll", - p_OPERATION_MODE = "NORMAL", - i_INCLK=clk50, - o_CLK=self.cd_sys_ps.clk, - i_ARESET=~rst_n, - i_CLKENA=0x3f, - i_EXTCLKENA=0xf, - i_FBIN=1, - i_PFDENA=1, - i_PLLENA=1, + p_BANDWIDTH_TYPE = "AUTO", + p_CLK0_DIVIDE_BY = 1, + p_CLK0_DUTY_CYCLE = 50, + p_CLK0_MULTIPLY_BY = 1, + p_CLK0_PHASE_SHIFT = "-10000", + p_COMPENSATE_CLOCK = "CLK0", + p_INCLK0_INPUT_FREQUENCY = 20000, + p_INTENDED_DEVICE_FAMILY = "MAX 10", + p_LPM_TYPE = "altpll", + p_OPERATION_MODE = "NORMAL", + i_INCLK = clk50, + o_CLK = self.cd_sys_ps.clk, + i_ARESET = ~rst_n, + i_CLKENA = 0x3f, + i_EXTCLKENA = 0xf, + i_FBIN = 1, + i_PFDENA = 1, + i_PLLENA = 1, ) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) @@ -69,18 +70,22 @@ class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de10lite.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) + # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = IS42S16320(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/community/targets/de1soc.py b/litex_boards/community/targets/de1soc.py index 455521f..22572a2 100755 --- a/litex_boards/community/targets/de1soc.py +++ b/litex_boards/community/targets/de1soc.py @@ -15,13 +15,13 @@ from litex.soc.integration.builder import * from litedram.modules import IS42S16320 from litedram.phy import GENSDRPHY -# CRG ------------------------------------------------------------------ +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform): - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # @@ -43,37 +43,41 @@ class _CRG(Module): self.comb += self.cd_sys.clk.eq(clk50) self.specials += \ Instance("ALTPLL", - p_BANDWIDTH_TYPE="AUTO", - p_CLK0_DIVIDE_BY=1, - p_CLK0_DUTY_CYCLE=50, - p_CLK0_MULTIPLY_BY=1, - p_CLK0_PHASE_SHIFT="-3000", - p_COMPENSATE_CLOCK="CLK0", - p_INCLK0_INPUT_FREQUENCY=20000, - p_OPERATION_MODE="ZERO_DELAY_BUFFER", - i_INCLK=clk50, - o_CLK=self.cd_sys_ps.clk, - i_ARESET=~rst_n, - i_CLKENA=0x3f, - i_EXTCLKENA=0xf, - i_FBIN=1, - i_PFDENA=1, - i_PLLENA=1, + p_BANDWIDTH_TYPE = "AUTO", + p_CLK0_DIVIDE_BY = 1, + p_CLK0_DUTY_CYCLE = 50, + p_CLK0_MULTIPLY_BY = 1, + p_CLK0_PHASE_SHIFT = "-3000", + p_COMPENSATE_CLOCK = "CLK0", + p_INCLK0_INPUT_FREQUENCY = 20000, + p_OPERATION_MODE = "ZERO_DELAY_BUFFER", + i_INCLK = clk50, + o_CLK = self.cd_sys_ps.clk, + i_ARESET = ~rst_n, + i_CLKENA = 0x3f, + i_EXTCLKENA = 0xf, + i_FBIN = 1, + i_PFDENA = 1, + i_PLLENA = 1, ) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) -# BaseSoC -------------------------------------------------------------- +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de1soc.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) + # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) # ISSI IS42S16320D-7TL @@ -82,7 +86,7 @@ class BaseSoC(SoCSDRAM): sdram_module.geom_settings, sdram_module.timing_settings) -# Build ---------------------------------------------------------------- +# Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC") diff --git a/litex_boards/community/targets/de2_115.py b/litex_boards/community/targets/de2_115.py index 3d82159..5749d34 100755 --- a/litex_boards/community/targets/de2_115.py +++ b/litex_boards/community/targets/de2_115.py @@ -15,13 +15,13 @@ from litex.soc.integration.builder import * from litedram.modules import IS42S16320 from litedram.phy import GENSDRPHY -# CRG ------------------------------------------------------------------ +# CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform): - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # @@ -43,46 +43,50 @@ class _CRG(Module): self.comb += self.cd_sys.clk.eq(clk50) self.specials += \ Instance("ALTPLL", - p_BANDWIDTH_TYPE="AUTO", - p_CLK0_DIVIDE_BY=1, - p_CLK0_DUTY_CYCLE=50, - p_CLK0_MULTIPLY_BY=1, - p_CLK0_PHASE_SHIFT="-3000", - p_COMPENSATE_CLOCK="CLK0", - p_INCLK0_INPUT_FREQUENCY=20000, - p_OPERATION_MODE="ZERO_DELAY_BUFFER", - i_INCLK=clk50, - o_CLK=self.cd_sys_ps.clk, - i_ARESET=~rst_n, - i_CLKENA=0x3f, - i_EXTCLKENA=0xf, - i_FBIN=1, - i_PFDENA=1, - i_PLLENA=1, + p_BANDWIDTH_TYPE = "AUTO", + p_CLK0_DIVIDE_BY = 1, + p_CLK0_DUTY_CYCLE = 50, + p_CLK0_MULTIPLY_BY = 1, + p_CLK0_PHASE_SHIFT = "-3000", + p_COMPENSATE_CLOCK = "CLK0", + p_INCLK0_INPUT_FREQUENCY = 20000, + p_OPERATION_MODE = "ZERO_DELAY_BUFFER", + i_INCLK = clk50, + o_CLK = self.cd_sys_ps.clk, + i_ARESET = ~rst_n, + i_CLKENA = 0x3f, + i_EXTCLKENA = 0xf, + i_FBIN = 1, + i_PFDENA = 1, + i_PLLENA = 1, ) self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) -# BaseSoC -------------------------------------------------------------- +# BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = de2_115.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) + # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) # ISSI IS42S16320D-7TL sdram_module = IS42S16320(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) -# Build ---------------------------------------------------------------- +# Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115") diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index 6c72e59..ca62838 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -45,11 +45,13 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs): platform = ecp5_evn.Platform(toolchain=toolchain) - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) - # crg + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) self.submodules.crg = crg @@ -69,8 +71,8 @@ def main(): cls = BaseSoC soc = cls(toolchain=args.toolchain, - sys_clk_freq=int(float(args.sys_clk_freq)), - x5_clk_freq=args.x5_clk_freq, + sys_clk_freq = int(float(args.sys_clk_freq)), + x5_clk_freq = args.x5_clk_freq, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index ad677bc..69e1b55 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -31,23 +31,23 @@ from litex_boards.platforms import aller class CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() clk100 = platform.request("clk100") self.submodules.pll = pll = S7PLL() pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk200, 200e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# AllerSoC ------------------------------------------------------------------------------------------ +# AllerSoC ----------------------------------------------------------------------------------------- class AllerSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x00000000 @@ -55,12 +55,14 @@ class AllerSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) + + # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width=32, - integrated_rom_size=0x10000, - integrated_sram_size=0x10000, - integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests - ident="Aller LiteX Test SoC", ident_version=True, + csr_data_width = 32, + integrated_rom_size = 0x10000, + integrated_sram_size = 0x10000, + integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests + ident = "Aller LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- @@ -75,26 +77,25 @@ class AllerSoC(SoCSDRAM): self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # SDRAM ------------------------------------------------------------------------------------ + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.A7DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq, - iodelay_clk_freq=200e6) + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6) + self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) - self.add_csr("ddrphy") + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") - platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.pcie_phy.cd_pcie.clk) + platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint @@ -128,11 +129,11 @@ class AllerSoC(SoCSDRAM): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() - self.rx_data = CSRStatus(8) + self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) + self.tx_data = CSRStorage(8) # # # diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index b27e666..5ed1d8f 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -26,9 +26,9 @@ from litex.soc.cores.hyperbus import HyperRAM # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform): - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # @@ -51,28 +51,28 @@ class _CRG(Module): clk_outs = Signal(5) self.specials += \ Instance("ALTPLL", - p_BANDWIDTH_TYPE="AUTO", - p_CLK0_DIVIDE_BY=6, - p_CLK0_DUTY_CYCLE=50, - p_CLK0_MULTIPLY_BY=25, - p_CLK0_PHASE_SHIFT="0", - p_CLK1_DIVIDE_BY=6, - p_CLK1_DUTY_CYCLE=50, - p_CLK1_MULTIPLY_BY=25, - p_CLK1_PHASE_SHIFT="-10000", - p_COMPENSATE_CLOCK="CLK0", - p_INCLK0_INPUT_FREQUENCY=83000, - p_INTENDED_DEVICE_FAMILY="MAX 10", - p_LPM_TYPE="altpll", - p_OPERATION_MODE="NORMAL", - i_INCLK=clk12, - o_CLK=clk_outs, - i_ARESET=0, - i_CLKENA=0x3f, - i_EXTCLKENA=0xf, - i_FBIN=1, - i_PFDENA=1, - i_PLLENA=1, + p_BANDWIDTH_TYPE = "AUTO", + p_CLK0_DIVIDE_BY = 6, + p_CLK0_DUTY_CYCLE = 50, + p_CLK0_MULTIPLY_BY = 25, + p_CLK0_PHASE_SHIFT = "0", + p_CLK1_DIVIDE_BY = 6, + p_CLK1_DUTY_CYCLE = 50, + p_CLK1_MULTIPLY_BY = 25, + p_CLK1_PHASE_SHIFT = "-10000", + p_COMPENSATE_CLOCK = "CLK0", + p_INCLK0_INPUT_FREQUENCY = 83000, + p_INTENDED_DEVICE_FAMILY = "MAX 10", + p_LPM_TYPE = "altpll", + p_OPERATION_MODE = "NORMAL", + i_INCLK = clk12, + o_CLK = clk_outs, + i_ARESET = 0, + i_CLKENA = 0x3f, + i_EXTCLKENA = 0xf, + i_FBIN = 1, + i_PFDENA = 1, + i_PLLENA = 1, ) self.comb += self.cd_sys.clk.eq(clk_outs[0]) self.comb += self.cd_sys_ps.clk.eq(clk_outs[1]) @@ -90,23 +90,29 @@ class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(50e6), **kwargs): assert sys_clk_freq == int(50e6) platform = c10lprefkit.Platform() + + # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) + # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024) + # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = MT48LC16M16(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) +# EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): mem_map = { diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index f700e24..367ca0b 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -32,16 +32,16 @@ from litex_boards.platforms import nereid class CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() clk100 = platform.request("clk100") self.submodules.pll = pll = S7PLL() pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_clk200, 200e6) self.comb += pll.reset.eq(platform.request("cpu_reset")) @@ -55,13 +55,15 @@ class NereidSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) + + # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width=32, - integrated_rom_size=0x10000, - integrated_sram_size=0x10000, - integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests - ident="Nereid LiteX Test SoC", ident_version=True, - with_uart=not with_pcie_uart) + csr_data_width = 32, + integrated_rom_size = 0x10000, + integrated_sram_size = 0x10000, + integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests + ident = "Nereid LiteX Test SoC", ident_version=True, + with_uart = not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -75,26 +77,25 @@ class NereidSoC(SoCSDRAM): self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # SDRAM ------------------------------------------------------------------------------------ + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.K7DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq, - iodelay_clk_freq=200e6) + self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6) + self.add_csr("ddrphy") sdram_module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800") self.register_sdram(self.ddrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) - self.add_csr("ddrphy") + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000) self.pcie_phy.cd_pcie.clk.attr.add("keep") platform.add_platform_command("create_clock -name pcie_clk -period 8 [get_nets pcie_clk]") - platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.pcie_phy.cd_pcie.clk) + platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # pcie endpoint @@ -128,11 +129,11 @@ class NereidSoC(SoCSDRAM): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() - self.rx_data = CSRStatus(8) + self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) + self.tx_data = CSRStorage(8) # # # diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index 763974a..c6f4e07 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -32,24 +32,24 @@ from litex_boards.platforms import tagus class CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() clk100 = platform.request("clk100") self.submodules.pll = pll = S7PLL() pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk200, 200e6) self.comb += pll.reset.eq(platform.request("rst")) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# NereidSoC ------------------------------------------------------------------------------------------ +# TagusSoC ----------------------------------------------------------------------------------------- class TagusSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x00000000 @@ -57,13 +57,15 @@ class TagusSoC(SoCSDRAM): def __init__(self, platform, with_pcie_uart=True): sys_clk_freq = int(100e6) + + # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width=32, - integrated_rom_size=0x10000, - integrated_sram_size=0x10000, - integrated_main_ram_size=0x10000, # FIXME: keep this for initial PCIe tests - ident="Tagus LiteX Test SoC", ident_version=True, - with_uart=not with_pcie_uart) + csr_data_width = 32, + integrated_rom_size = 0x10000, + integrated_sram_size = 0x10000, + integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests + ident = "Tagus LiteX Test SoC", ident_version=True, + with_uart = not with_pcie_uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -77,17 +79,18 @@ class TagusSoC(SoCSDRAM): self.submodules.xadc = xadc.XADC() self.add_csr("xadc") - # SDRAM ------------------------------------------------------------------------------------ + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = s7ddrphy.A7DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq, - iodelay_clk_freq=200e6) + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6) + self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) - self.add_csr("ddrphy") # PCIe ------------------------------------------------------------------------------------- # pcie phy @@ -130,11 +133,11 @@ class TagusSoC(SoCSDRAM): def __init__(self, uart): self.rx_valid = CSRStatus() self.rx_ready = CSR() - self.rx_data = CSRStatus(8) + self.rx_data = CSRStatus(8) self.tx_valid = CSR() self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) + self.tx_data = CSRStorage(8) # # # diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index e7d202d..6524b0b 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -26,10 +26,10 @@ from liteeth.mac import LiteEthMAC class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_init = ClockDomain() - self.clock_domains.cd_por = ClockDomain(reset_less=True) - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_init = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -44,12 +44,12 @@ class _CRG(Module): # clk / rst clk12 = platform.request("clk12") - rst = platform.request("user_btn", 0) + rst = platform.request("user_btn", 0) platform.add_period_constraint(clk12, 1e9/12e6) # power on reset por_count = Signal(16, reset=2**16-1) - por_done = Signal() + por_done = Signal() self.comb += self.cd_por.clk.eq(ClockSignal()) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -62,20 +62,20 @@ class _CRG(Module): pll.create_clkout(self.cd_init, 25e6) self.specials += [ Instance("ECLKBRIDGECS", - i_CLK0=self.cd_sys2x_i.clk, - i_SEL=0, - o_ECSOUT=sys2x_clk_ecsout, + i_CLK0 = self.cd_sys2x_i.clk, + i_SEL = 0, + o_ECSOUT = sys2x_clk_ecsout, ), Instance("ECLKSYNCB", - i_ECLKI=sys2x_clk_ecsout, - i_STOP=self.stop, - o_ECLKO=self.cd_sys2x.clk), + i_ECLKI = sys2x_clk_ecsout, + i_STOP = self.stop, + o_ECLKO = self.cd_sys2x.clk), Instance("CLKDIVF", - p_DIV="2.0", - i_ALIGNWD=0, - i_CLKI=self.cd_sys2x.clk, - i_RST=self.cd_sys2x.rst, - o_CDIVX=self.cd_sys.clk), + p_DIV = "2.0", + i_ALIGNWD = 0, + i_CLKI = self.cd_sys2x.clk, + i_RST = self.cd_sys2x.rst, + o_CDIVX = self.cd_sys.clk), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst), AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst) ] @@ -88,25 +88,26 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): platform = trellisboard.Platform(toolchain=toolchain) + + # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - **kwargs) + integrated_rom_size=integrated_rom_size, + **kwargs) - # crg - crg = _CRG(platform, sys_clk_freq) - self.submodules.crg = crg + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) - # sdram + # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) - self.comb += crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) sdram_module = MT41J256M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # EthernetSoC --------------------------------------------------------------------------------------