diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index 23aec6c..27d3368 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import argparse import sys from migen import * @@ -47,21 +48,19 @@ class CRG(Module): self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# AllerSoC ----------------------------------------------------------------------------------------- +# PCIeSoC ----------------------------------------------------------------------------------------- -class AllerSoC(SoCSDRAM): +class PCIeSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 - def __init__(self, platform, with_pcie_uart=True): + def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width = 32, - integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests - ident = "Aller LiteX Test SoC", ident_version=True, - with_uart=not with_pcie_uart) + ident = "LiteX SoC on Tagus", ident_version=True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -121,61 +120,6 @@ class AllerSoC(SoCSDRAM): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) - # pcie_uart - if with_pcie_uart: - class PCIeUART(Module, AutoCSR): - def __init__(self, uart): - self.rx_valid = CSRStatus() - self.rx_ready = CSR() - self.rx_data = CSRStatus(8) - - self.tx_valid = CSR() - self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) - - # # # - - # cpu to pcie - self.comb += [ - self.rx_valid.status.eq(uart.sink.valid), - uart.sink.ready.eq(self.rx_ready.re), - self.rx_data.status.eq(uart.sink.data), - ] - - # pcie to cpu - self.sync += [ - If(self.tx_valid.re, - uart.source.valid.eq(1) - ).Elif(uart.source.ready, - uart.source.valid.eq(0) - ) - ] - self.comb += [ - self.tx_ready.status.eq(~uart.source.valid), - uart.source.data.eq(self.tx_data.storage) - ] - - uart_interface = RS232PHYInterface() - self.submodules.uart = UART(uart_interface) - self.add_csr("uart") - self.add_interrupt("uart") - self.submodules.pcie_uart = PCIeUART(uart_interface) - self.add_csr("pcie_uart") - - # Leds ------------------------------------------------------------------------------------- - # led blinking (sys) - sys_counter = Signal(32) - self.sync.sys += sys_counter.eq(sys_counter + 1) - - pcie_counter = Signal(32) - self.sync.pcie += pcie_counter.eq(pcie_counter + 1) - - self.comb += [ - platform.request("user_led", 0).eq(~self.pcie_phy._lnk_up.status), - platform.request("user_led", 1).eq(~pcie_counter[26]), - platform.request("user_led", 2).eq(~sys_counter[26]), - ] - def generate_software_header(self, filename): csr_header = get_csr_header(self.csr_regions, self.constants, @@ -186,13 +130,19 @@ class AllerSoC(SoCSDRAM): # Build -------------------------------------------------------------------------------------------- def main(): - platform = aller.Platform() - soc = AllerSoC(platform) - builder = Builder(soc, output_dir="aller", csr_csv="aller/csr.csv", - compile_gateware=not "no-compile" in sys.argv[1:]) - vns = builder.build(build_name="aller") - soc.generate_software_header("aller/csr.h") + parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + args.uart_name = "crossover" + args.csr_data_width = 32 + + platform = aller.Platform() + soc = PCIeSoC(platform, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + vns = builder.build() + soc.generate_software_header("csr.h") if __name__ == "__main__": main() diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index 8a9265c..99eaad6 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import argparse import sys from migen import * @@ -18,7 +19,6 @@ from litex.soc.cores.uart import * from litex.soc.integration.cpu_interface import get_csr_header from litedram.modules import MT8KTF51264 -from litedram.modules import _TechnologyTimings, _SpeedgradeTimings from litedram.phy import s7ddrphy from litepcie.phy.s7pciephy import S7PCIEPHY @@ -39,29 +39,27 @@ class CRG(Module): clk100 = platform.request("clk100") self.submodules.pll = pll = S7PLL() + self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_clk200, 200e6) - self.comb += pll.reset.eq(platform.request("cpu_reset")) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# NereidSoC ---------------------------------------------------------------------------------------- +# PCIeSoC ----------------------------------------------------------------------------------------- -class NereidSoC(SoCSDRAM): +class PCIeSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 - def __init__(self, platform, with_pcie_uart=True): + def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width = 32, - integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests - ident = "Nereid LiteX Test SoC", ident_version=True, - with_uart = not with_pcie_uart) + ident = "LiteX SoC on Nereid", ident_version=True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -121,58 +119,6 @@ class NereidSoC(SoCSDRAM): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) - # pcie uart - if with_pcie_uart: - class PCIeUART(Module, AutoCSR): - def __init__(self, uart): - self.rx_valid = CSRStatus() - self.rx_ready = CSR() - self.rx_data = CSRStatus(8) - - self.tx_valid = CSR() - self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) - - # # # - - # cpu to pcie - self.comb += [ - self.rx_valid.status.eq(uart.sink.valid), - uart.sink.ready.eq(self.rx_ready.re), - self.rx_data.status.eq(uart.sink.data), - ] - - # pcie to cpu - self.sync += [ - If(self.tx_valid.re, - uart.source.valid.eq(1) - ).Elif(uart.source.ready, - uart.source.valid.eq(0) - ) - ] - self.comb += [ - self.tx_ready.status.eq(~uart.source.valid), - uart.source.data.eq(self.tx_data.storage) - ] - - uart_interface = RS232PHYInterface() - self.submodules.uart = UART(uart_interface) - self.add_csr("uart") - self.add_interrupt("uart") - self.submodules.pcie_uart = PCIeUART(uart_interface) - self.add_csr("pcie_uart") - - # Leds ------------------------------------------------------------------------------------- - # led blinking (sys) - sys_counter = Signal(32) - self.sync.sys += sys_counter.eq(sys_counter + 1) - rgb = platform.request("rgb_led") - self.comb += [ - rgb.r.eq(1), - rgb.g.eq(sys_counter[26]), - rgb.b.eq(1), - ] - def generate_software_header(self, filename): csr_header = get_csr_header(self.csr_regions, self.constants, @@ -183,13 +129,19 @@ class NereidSoC(SoCSDRAM): # Build -------------------------------------------------------------------------------------------- def main(): - platform = nereid.Platform() - soc = NereidSoC(platform) - builder = Builder(soc, output_dir="nereid", csr_csv="nereid/csr.csv", - compile_gateware=not "no-compile" in sys.argv[1:]) - vns = builder.build(build_name="nereid") - soc.generate_software_header("nereid/csr.h") + parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + args.uart_name = "crossover" + args.csr_data_width = 32 + + platform = nereid.Platform() + soc = PCIeSoC(platform, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + vns = builder.build() + soc.generate_software_header("csr.h") if __name__ == "__main__": main() diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index 0111fd6..ae1f132 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -2,9 +2,9 @@ # This file is Copyright (c) 2018-2019 Rohit Singh # This file is Copyright (c) 2019 Florent Kermarrec - # License: BSD +import argparse import sys from migen import * @@ -40,30 +40,28 @@ class CRG(Module): clk100 = platform.request("clk100") self.submodules.pll = pll = S7PLL() + self.comb += pll.reset.eq(platform.request("rst")) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) - self.comb += pll.reset.eq(platform.request("rst")) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -# TagusSoC ----------------------------------------------------------------------------------------- +# PCIeSoC ----------------------------------------------------------------------------------------- -class TagusSoC(SoCSDRAM): +class PCIeSoC(SoCSDRAM): SoCSDRAM.mem_map["csr"] = 0x80000000 SoCSDRAM.mem_map["rom"] = 0x20000000 - def __init__(self, platform, with_pcie_uart=True): + def __init__(self, platform, **kwargs): sys_clk_freq = int(100e6) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, - csr_data_width = 32, - integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests - ident = "Tagus LiteX Test SoC", ident_version=True, - with_uart = not with_pcie_uart) + ident = "LiteX SoC on Tagus", ident_version=True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq) @@ -87,8 +85,8 @@ class TagusSoC(SoCSDRAM): self.add_csr("ddrphy") sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, - sdram_module.geom_settings, - sdram_module.timing_settings) + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # PCIe ------------------------------------------------------------------------------------- # pcie phy @@ -123,57 +121,6 @@ class TagusSoC(SoCSDRAM): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) - # pcie_uart - if with_pcie_uart: - class PCIeUART(Module, AutoCSR): - def __init__(self, uart): - self.rx_valid = CSRStatus() - self.rx_ready = CSR() - self.rx_data = CSRStatus(8) - - self.tx_valid = CSR() - self.tx_ready = CSRStatus() - self.tx_data = CSRStorage(8) - - # # # - - # cpu to pcie - self.comb += [ - self.rx_valid.status.eq(uart.sink.valid), - uart.sink.ready.eq(self.rx_ready.re), - self.rx_data.status.eq(uart.sink.data), - ] - - # pcie to cpu - self.sync += [ - If(self.tx_valid.re, - uart.source.valid.eq(1) - ).Elif(uart.source.ready, - uart.source.valid.eq(0) - ) - ] - self.comb += [ - self.tx_ready.status.eq(~uart.source.valid), - uart.source.data.eq(self.tx_data.storage) - ] - - uart_interface = RS232PHYInterface() - self.submodules.uart = UART(uart_interface) - self.add_csr("uart") - self.add_interrupt("uart") - self.submodules.pcie_uart = PCIeUART(uart_interface) - self.add_csr("pcie_uart") - - # Leds ------------------------------------------------------------------------------------- - # led blinking (sys) - sys_counter = Signal(32) - self.sync.sys += sys_counter.eq(sys_counter + 1) - self.comb += [ - platform.request("user_led", 0).eq(1), - platform.request("user_led", 1).eq(sys_counter[26]), - platform.request("user_led", 2).eq(1), - ] - def generate_software_header(self, filename): csr_header = get_csr_header(self.csr_regions, self.constants, @@ -184,13 +131,19 @@ class TagusSoC(SoCSDRAM): # Build -------------------------------------------------------------------------------------------- def main(): - platform = tagus.Platform() - soc = TagusSoC(platform) - builder = Builder(soc, output_dir="tagus", csr_csv="tagus/csr.csv", - compile_gateware=not "no-compile" in sys.argv[1:]) - vns = builder.build(build_name="tagus") - soc.generate_software_header("tagus/csr.h") + parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + args.uart_name = "crossover" + args.csr_data_width = 32 + + platform = tagus.Platform() + soc = PCIeSoC(platform, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + vns = builder.build() + soc.generate_software_header("csr.h") if __name__ == "__main__": main()