From f9939532b68b6af334cdebe75ae5cba040fdc408 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 May 2020 12:15:52 +0200 Subject: [PATCH] targets/pcie: update LitePCIe constraints. --- litex_boards/targets/acorn_cle_215.py | 1 + litex_boards/targets/aller.py | 1 + litex_boards/targets/nereid.py | 1 + litex_boards/targets/tagus.py | 1 + 4 files changed, 4 insertions(+) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 5a643a8..6f1b092 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -118,6 +118,7 @@ class PCIeSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 64, bar0_size = 0x20000) + self.pcie_phy.add_timing_constraints(platform) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") self.comb += platform.request("pcie_clkreq_n").eq(0) diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 204841a..af4bfa9 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -119,6 +119,7 @@ class PCIeSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, bar0_size = 0x20000) + self.pcie_phy.add_timing_constraints(platform) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index b9db14b..3672abb 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -117,6 +117,7 @@ class PCIeSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, bar0_size = 0x20000) + self.pcie_phy.add_timing_constraints(platform) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index d5ec4e7..ef6c36f 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -117,6 +117,7 @@ class PCIeSoC(SoCCore): self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, bar0_size = 0x20000) + self.pcie_phy.add_timing_constraints(platform) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy")