From fad45b45c1765db710e0caa5321cb9a95ba06567 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 11 Apr 2024 15:12:17 +0200 Subject: [PATCH] targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart --- litex_boards/targets/limesdr_mini_v2.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/limesdr_mini_v2.py b/litex_boards/targets/limesdr_mini_v2.py index e123dca..8a2fd0c 100755 --- a/litex_boards/targets/limesdr_mini_v2.py +++ b/litex_boards/targets/limesdr_mini_v2.py @@ -11,6 +11,11 @@ # litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg # litex_term crossover +# loading a demo +# ./limesdr_mini_v2.py --integrated-main-ram-size 0x8000 --load --build --uart-name=jtag_uart +# litex_bare_metal_demo --build-path build/limesdr_mini_v2 +# litex_term jtag --jtag-config=openocd_limesdr_mini_v2.cfg --kernel demo.bin + from migen import * from litex.gen import * @@ -75,8 +80,9 @@ class BaseSoC(SoCCore): platform = limesdr_mini_v2.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- - kwargs["uart_name"] = "crossover" - kwargs["with_jtagbone"] = True + if kwargs["uart_name"] != "jtag_uart": + kwargs["uart_name"] = "crossover" + kwargs["with_jtagbone"] = True SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on LimeSDR-Mini-V2", **kwargs) # CRG --------------------------------------------------------------------------------------