diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
index 286c008..65496a4 100755
--- a/litex_boards/targets/lattice_crosslink_nx_evn.py
+++ b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
     }
     def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser=True, **kwargs):
         platform = crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
-        platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
 
         # Disable Integrated SRAM since we want to instantiate LRAM specifically for it
         kwargs["integrated_sram_size"] = 0