diff --git a/litex_boards/targets/digilent_basys3.py b/litex_boards/targets/digilent_basys3.py
index 97b6fca..542fd65 100755
--- a/litex_boards/targets/digilent_basys3.py
+++ b/litex_boards/targets/digilent_basys3.py
@@ -29,7 +29,7 @@ class _CRG(Module):
         self.clock_domains.cd_vga       = ClockDomain(reset_less=True)
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
-        self.comb += pll.reset.eq(~platform.request("user_btnc") | self.rst)
+        self.comb += pll.reset.eq(platform.request("user_btnc") | self.rst)
 
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)