diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 983c70f..5a35dc1 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -68,9 +68,9 @@ class CRG(Module):
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-# PCIeSoC -----------------------------------------------------------------------------------------
+# BaseSoC -----------------------------------------------------------------------------------------
 
-class PCIeSoC(SoCCore):
+class BaseSoC(SoCCore):
     def __init__(self, platform, **kwargs):
         sys_clk_freq = int(100e6)
 
@@ -171,7 +171,7 @@ def main():
     args.csr_data_width = 32
 
     platform = acorn_cle_215.Platform()
-    soc      = PCIeSoC(platform, **soc_sdram_argdict(args))
+    soc      = BaseSoC(platform, **soc_sdram_argdict(args))
     builder  = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index a1f276b..e2ee2ec 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -51,9 +51,9 @@ class CRG(Module):
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-# PCIeSoC -----------------------------------------------------------------------------------------
+# BaseSoC -----------------------------------------------------------------------------------------
 
-class PCIeSoC(SoCCore):
+class BaseSoC(SoCCore):
     def __init__(self, platform, **kwargs):
         sys_clk_freq = int(100e6)
 
@@ -152,7 +152,7 @@ def main():
     args.csr_data_width = 32
 
     platform = aller.Platform()
-    soc      = PCIeSoC(platform, **soc_sdram_argdict(args))
+    soc      = BaseSoC(platform, **soc_sdram_argdict(args))
     builder  = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index c5d4308..511815e 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -48,9 +48,9 @@ class CRG(Module):
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-# PCIeSoC -----------------------------------------------------------------------------------------
+# BaseSoC -----------------------------------------------------------------------------------------
 
-class PCIeSoC(SoCCore):
+class BaseSoC(SoCCore):
     def __init__(self, platform, **kwargs):
         sys_clk_freq = int(100e6)
 
@@ -143,7 +143,7 @@ def main():
     args.csr_data_width = 32
 
     platform = nereid.Platform()
-    soc      = PCIeSoC(platform, **soc_sdram_argdict(args))
+    soc      = BaseSoC(platform, **soc_sdram_argdict(args))
     builder  = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index d4068a3..e3c0cee 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -51,9 +51,9 @@ class CRG(Module):
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
-# PCIeSoC -----------------------------------------------------------------------------------------
+# BaseSoC -----------------------------------------------------------------------------------------
 
-class PCIeSoC(SoCCore):
+class BaseSoC(SoCCore):
     def __init__(self, platform, **kwargs):
         sys_clk_freq = int(100e6)
 
@@ -152,7 +152,7 @@ def main():
     args.csr_data_width = 32
 
     platform = tagus.Platform()
-    soc      = PCIeSoC(platform, **soc_sdram_argdict(args))
+    soc      = BaseSoC(platform, **soc_sdram_argdict(args))
     builder  = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)