From fd1e655700a5c1b74ff80900253f4b546fcadf01 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Jan 2020 10:28:09 +0100 Subject: [PATCH] targets: cleanup EthernetSoC --- litex_boards/community/targets/ac701.py | 32 +++++++---- litex_boards/official/targets/arty.py | 58 +++++++++++++++++--- litex_boards/official/targets/genesys2.py | 21 +++++-- litex_boards/official/targets/kc705.py | 18 ++++-- litex_boards/official/targets/kcu105.py | 20 ++++--- litex_boards/official/targets/nexys4ddr.py | 22 +++++--- litex_boards/official/targets/nexys_video.py | 17 ++++-- litex_boards/official/targets/simple.py | 9 ++- litex_boards/official/targets/versa_ecp5.py | 9 ++- litex_boards/partner/targets/c10lprefkit.py | 24 ++++---- litex_boards/partner/targets/netv2.py | 48 ++++++++-------- litex_boards/partner/targets/trellisboard.py | 15 +++-- 12 files changed, 199 insertions(+), 94 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index ad9490a..4bea97f 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -82,9 +82,12 @@ class EthernetSoC(BaseSoC): # RGMII Ethernet PHY ----------------------------------------------------------------------- if phy == "rgmii": - self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( @@ -94,25 +97,27 @@ class EthernetSoC(BaseSoC): # 1000BaseX Ethernet PHY ------------------------------------------------------------------- if phy == "1000basex": + # phy self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) qpll_settings = QPLLSettings( - refclksel=0b001, - fbdiv=4, - fbdiv_45=5, - refclk_div=1) + refclksel = 0b001, + fbdiv = 4, + fbdiv_45 = 5, + refclk_div = 1) refclk125 = self.platform.request("gtp_refclk") refclk125_se = Signal() self.specials += \ Instance("IBUFDS_GTE2", - i_CEB=0, - i_I=refclk125.p, - i_IB=refclk125.n, - o_O=refclk125_se) + i_CEB = 0, + i_I = refclk125.p, + i_IB = refclk125.n, + o_O = refclk125_se) qpll = QPLL(refclk125_se, qpll_settings) self.submodules += qpll self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq) + # timing constraints self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6) self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6) self.platform.add_false_path_constraints( @@ -121,8 +126,11 @@ class EthernetSoC(BaseSoC): self.ethphy.rxoutclk) # Ethernet MAC ----------------------------------------------------------------------------- - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 1e774e3..7ec6afb 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -19,6 +19,8 @@ from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII from liteeth.mac import LiteEthMAC +from liteeth.core import LiteEthUDPIPCore +from liteeth.frontend.etherbone import LiteEthEtherbone # CRG ---------------------------------------------------------------------------------------------- @@ -80,24 +82,60 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) +# EtherboneSoC ------------------------------------------------------------------------------------- + +class EtherboneSoC(BaseSoC): + def __init__(self, **kwargs): + BaseSoC.__init__(self, **kwargs) + + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + # core + self.submodules.ethcore = LiteEthUDPIPCore( + phy = self.ethphy, + mac_address = 0x10e2d5000000, + ip_address = "192.168.1.50", + clk_freq = self.clk_freq) + # etherbone + self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) + self.add_wb_master(self.etherbone.wishbone.bus) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) + # Build -------------------------------------------------------------------------------------------- def main(): @@ -105,11 +143,13 @@ def main(): builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") args = parser.parse_args() + assert not (args.with_ethernet and args.with_etherbone) cls = EthernetSoC if args.with_ethernet else BaseSoC + cls = EtherboneSoC if args.with_etherbone else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args)) diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index b3c596c..c9fa450 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -58,7 +58,9 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41J256M16(self.clk_freq, "1:4") - self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) + self.register_sdram(self.ddrphy, + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # EthernetSoC -------------------------------------------------------------------------------------- @@ -71,16 +73,23 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index 0cbf789..24ccf54 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -75,16 +75,24 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), - self.platform.request("eth"), clk_freq=self.clk_freq) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth"), + clk_freq = self.clk_freq) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index 2accee5..d2e342e 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -110,17 +110,25 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + # Ethernet --------------------------------------------------------------------------------- + # phy self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, - self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( @@ -128,8 +136,6 @@ class EthernetSoC(BaseSoC): self.ethphy.cd_eth_rx.clk, self.ethphy.cd_eth_tx.clk) - self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 6ce90cb..14a469a 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -77,24 +77,30 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index bce71af..57cca43 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -77,16 +77,23 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/simple.py b/litex_boards/official/targets/simple.py index 0dc5df1..fa74077 100755 --- a/litex_boards/official/targets/simple.py +++ b/litex_boards/official/targets/simple.py @@ -24,6 +24,7 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) @@ -38,9 +39,13 @@ class EthernetSoC(BaseSoC): def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) - self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), - platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") + # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 41bedb8..29b1f88 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -105,19 +105,26 @@ class EthernetSoC(BaseSoC): def __init__(self, toolchain="diamond", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) + # Ethernet --------------------------------------------------------------------------------- + # phy self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") + # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index 7965c67..761f25d 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -123,27 +123,31 @@ class EthernetSoC(BaseSoC): def __init__(self, eth_port=0, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks", eth_port), - self.platform.request("eth", eth_port)) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_tx.clk, self.ethphy.crg.cd_eth_rx.clk ) - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index 8f7e451..57c5196 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -23,27 +23,23 @@ from liteeth.mac import LiteEthMAC class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_clk100 = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk100 = ClockDomain() + self.clock_domains.cd_eth = ClockDomain() # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-1) pll.register_clkin(platform.request("clk50"), 50e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) - pll.create_clkout(self.cd_clk100, 100e6) - pll.create_clkout(self.cd_eth, 50e6) + pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk100, 100e6) + pll.create_clkout(self.cd_eth, 50e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) @@ -82,26 +78,30 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/50e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index 80b79b0..ac3f22b 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -111,21 +111,26 @@ class EthernetSoC(BaseSoC): def __init__(self, toolchain="diamond", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) + # Ethernet --------------------------------------------------------------------------------- + # phy self.submodules.ethphy = LiteEthPHYRGMII( - self.platform.request("eth_clocks"), - self.platform.request("eth")) + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") + # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) # Build --------------------------------------------------------------------------------------------