From fd4f9ac1863f555b2b0ae63cad9641216bf34dcd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Aug 2024 12:17:24 +0200 Subject: [PATCH] targets: Use KILOBYTE/MEGABYTE constants when possible. --- litex_boards/targets/alchitry_mojo.py | 2 +- litex_boards/targets/aliexpress_xc7k70t.py | 2 +- litex_boards/targets/alinx_axu2cga.py | 4 ++-- litex_boards/targets/antmicro_datacenter_ddr4_test_board.py | 2 +- litex_boards/targets/antmicro_lpddr4_test_board.py | 2 +- litex_boards/targets/digilent_arty_z7.py | 4 ++-- litex_boards/targets/digilent_cmod_a7.py | 2 +- litex_boards/targets/digilent_nexys4.py | 2 +- litex_boards/targets/digilent_zedboard.py | 5 ++--- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 4 ++-- litex_boards/targets/lattice_crosslink_nx_vip.py | 2 +- litex_boards/targets/micronova_mercury2.py | 2 +- litex_boards/targets/quicklogic_quickfeather.py | 2 +- litex_boards/targets/qwertyembedded_beaglewire.py | 2 +- litex_boards/targets/trenz_c10lprefkit.py | 2 +- litex_boards/targets/trenz_te0725.py | 2 +- litex_boards/targets/xilinx_kv260.py | 4 ++-- litex_boards/targets/xilinx_zcu216.py | 4 ++-- litex_boards/targets/xilinx_zybo_z7.py | 4 ++-- 19 files changed, 26 insertions(+), 27 deletions(-) diff --git a/litex_boards/targets/alchitry_mojo.py b/litex_boards/targets/alchitry_mojo.py index 180d249..06f2553 100755 --- a/litex_boards/targets/alchitry_mojo.py +++ b/litex_boards/targets/alchitry_mojo.py @@ -126,7 +126,7 @@ class BaseSoC(SoCCore): self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC32M8(sys_clk_freq, sdram_rate), - l2_cache_size = kwargs.get("l2_size", 1024) + l2_cache_size = kwargs.get("l2_size", 1 * KILOBYTE) ) # HDMI Options ----------------------------------------------------------------------------- diff --git a/litex_boards/targets/aliexpress_xc7k70t.py b/litex_boards/targets/aliexpress_xc7k70t.py index b65e0c0..8d2b7af 100755 --- a/litex_boards/targets/aliexpress_xc7k70t.py +++ b/litex_boards/targets/aliexpress_xc7k70t.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): self.add_sdram("sdram", phy = self.sdrphy, module = W9812G6JB(sys_clk_freq, sdram_rate), - l2_cache_size = kwargs.get("l2_size", 1024) + l2_cache_size = kwargs.get("l2_size", 1 * KILOBYTE) ) # HDMI Options ----------------------------------------------------------------------------- diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index a08aa6a..a3fff88 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -85,11 +85,11 @@ class BaseSoC(SoCCore): self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 1 * 1024 * 1024 * 1024) # DDR + size = 1 * GIGABYTE) # DDR ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 512 * 1024 * 1024 // 8, + size = 512 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 1199880127 diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 1e8a4d4..a4d341c 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -118,7 +118,7 @@ class BaseSoC(SoCCore): # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index 79f58ac..e130959 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 04be70a..682fd65 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -103,11 +103,11 @@ class BaseSoC(SoCCore): self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) + size = 512 * MEGABYTE - self.cpu.mem_map["sram"]) ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 256 * 1024 * 1024 // 8, + size = 256 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687 diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 4a7424b..ca4dae0 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -119,7 +119,7 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Digilent CmodA7", **kwargs) # Async RAM -------------------------------------------------------------------------------- - addAsyncSram(self,platform,"main_ram", 0x40000000, 512*1024) + addAsyncSram(self,platform,"main_ram", 0x40000000, 512 * KILOBYTE) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/digilent_nexys4.py b/litex_boards/targets/digilent_nexys4.py index e9acb35..97cb2a1 100755 --- a/litex_boards/targets/digilent_nexys4.py +++ b/litex_boards/targets/digilent_nexys4.py @@ -151,7 +151,7 @@ class CellularRAM(LiteXModule): ######################## def addCellularRAM(soc, platform, name, origin): - size = 16*1024*1024 + size = 16 * MEGABYTE ram_bus = wishbone.Interface(data_width=soc.bus.data_width) ram = CellularRAM(soc,platform) soc.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode="rw")) diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 9f59d57..1baa926 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -50,7 +50,6 @@ class _CRG(LiteXModule): class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs): platform = digilent_zedboard.Platform() @@ -71,11 +70,11 @@ class BaseSoC(SoCCore): self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) + size = 512 * MEGABYTE - self.cpu.mem_map["sram"]) ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 256 * 1024 * 1024 // 8, + size = 256 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687 diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index dab549c..f78203e 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -75,8 +75,8 @@ class BaseSoC(SoCCore): if with_hyperram: # HyperRAM Parameters. hyperram_device = "W958D6NW" - hyperram_size = 32*1024*1024 - hyperram_cache_size = 16*1024 + hyperram_size = 32 * MEGABYTE + hyperram_cache_size = 16 * KILOBYTE # HyperRAM Bus/Slave Interface. hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word") diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 325bf1e..c7d6366 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -84,7 +84,7 @@ class BaseSoC(SoCCore): size=size)) else: # Use HyperRAM generic PHY as SRAM ----------------------------------------------------- - size = 8*1024 * KILOBYTE + size = 8 * MEGABYTE hr_pads = platform.request("hyperram", int(hyperram)) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py index 01cad51..8406efa 100755 --- a/litex_boards/targets/micronova_mercury2.py +++ b/litex_boards/targets/micronova_mercury2.py @@ -118,7 +118,7 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on MicroNova Mercury2", **kwargs) # Async RAM -------------------------------------------------------------------------------- - addAsyncSram(self,platform,"main_ram", 0x40000000, 512*1024) + addAsyncSram(self,platform,"main_ram", 0x40000000, 512 * KILOBYTE) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index ba51d72..c6cf7eb 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -70,7 +70,7 @@ class BaseSoC(SoCCore): ) self.bus.add_region("rom", SoCRegion( origin = self.mem_map["rom"], - size = 4 * 128 * 1024, + size = 4 * 128 * KILOBYTE, linker = True) ) diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index b976b23..3a5744f 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC32M8(sys_clk_freq, "1:1"), - l2_cache_size = kwargs.get("l2_size", 1024) + l2_cache_size = kwargs.get("l2_size", 1 * KILOBYTE) ) # SPI Flash -------------------------------------------------------------------------------- diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index db5aff2..88ec800 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -73,7 +73,7 @@ class BaseSoC(SoCCore): # HyperRam --------------------------------------------------------------------------------- self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py index 84d9656..e254c83 100755 --- a/litex_boards/targets/trenz_te0725.py +++ b/litex_boards/targets/trenz_te0725.py @@ -45,7 +45,7 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Trenz TE0725 Board", **kwargs) # Use HyperRAM generic PHY as SRAM --------------------------------------------------------- - size = int((64*1024*1024) / 8) + size = int((64 * MEGABYTE) / 8) hr_pads = platform.request("hyperram", 0) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size)) diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index c46c512..d7d71b5 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -127,11 +127,11 @@ class BaseSoC(SoCCore): self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 2 * 1024 * 1024 * 1024) # DDR + size = 2 * GIGABYTE) # DDR ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 512 * 1024 * 1024 // 8, + size = 512 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 1333333008 diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index a2b4b12..4c6e992 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -108,11 +108,11 @@ class BaseSoC(SoCCore): self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 2 * 1024 * 1024 * 1024) # DDR + size = 2 * GIGABYTE) # DDR ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 512 * 1024 * 1024 // 8, + size = 512 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 1200000000 diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index 86e344a..167e54c 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -74,11 +74,11 @@ class BaseSoC(SoCCore): #TODO memory size dependend on board variant self.bus.add_region("sram", SoCRegion( origin = self.cpu.mem_map["sram"], - size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"]) + size = 512 * MEGABYTE - self.cpu.mem_map["sram"]) ) self.bus.add_region("rom", SoCRegion( origin = self.cpu.mem_map["rom"], - size = 256 * 1024 * 1024 // 8, + size = 256 * MEGABYTE // 8, linker = True) ) self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687