xilinx_zc706: Review/Minor changes.

litex_boards/platforms/xilinx_zc706.py

@@ -12,7 +12,7 @@ from litex.build.openfpgaloader import OpenFPGALoader
 
 _io = [
     # Clk / Rst.
-    ("sysclk", 0,
+    ("clk200", 0,
         Subsignal("p", Pins("H9"), IOStandard("LVDS")),
         Subsignal("n", Pins("G9"), IOStandard("LVDS")),
     ),
@@ -34,17 +34,17 @@ _io = [
     ("user_btn_r", 0, Pins("R27"),  IOStandard("LVCMOS25")),
 
     # Switches.
-    ("user_dip_btn", 3, Pins("AJ13"), IOStandard("LVCMOS25")),
-    ("user_dip_btn", 2, Pins("AC17"), IOStandard("LVCMOS25")),
-    ("user_dip_btn", 1, Pins("AC16"), IOStandard("LVCMOS25")),
     ("user_dip_btn", 0, Pins("AB17"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 1, Pins("AC16"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 2, Pins("AC17"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 3, Pins("AJ13"), IOStandard("LVCMOS25")),
 
     # SMA.
     ("user_sma_clock", 0,
-        Subsignal("p", Pins("AD18"), IOStandard("LVDS_25"),
-            Misc("DIFF_TERM=TRUE")),
-        Subsignal("n", Pins("AD19"), IOStandard("LVDS_25"),
-            Misc("DIFF_TERM=TRUE")),
+        Subsignal("p", Pins("AD18")),
+        Subsignal("n", Pins("AD19")),
+        IOStandard("LVDS_25"),
+        Misc("DIFF_TERM=TRUE")
     ),
     ("user_sma_clock_p", Pins("AD18"), IOStandard("LVCMOS25")),
     ("user_sma_clock_n", Pins("AD19"), IOStandard("LVCMOS25")),
@@ -82,6 +82,7 @@ _io = [
     ),
 
     # SFP.
+    ("sfp_tx_disable_n", 0, Pins("AA18"), IOStandard("LVCMOS25")),
     ("sfp", 0,
         Subsignal("txp", Pins("W4")),
         Subsignal("txn", Pins("W3")),
@@ -96,7 +97,6 @@ _io = [
         Subsignal("p", Pins("Y6")),
         Subsignal("n", Pins("Y5")),
     ),
-    ("sfp_tx_disable_n", 0, Pins("AA18"), IOStandard("LVCMOS25")),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------
@@ -323,7 +323,7 @@ _connectors = [
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(Xilinx7SeriesPlatform):
-    default_clk_name   = "sysclk"
+    default_clk_name   = "clk200"
     default_clk_period = 1e9/200e6
 
     def __init__(self, toolchain="vivado"):
@@ -334,4 +334,4 @@ class Platform(Xilinx7SeriesPlatform):
 
     def do_finalize(self, fragment):
         Xilinx7SeriesPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("sysclk", loose=True), 1e9/200e6)
+        self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)

litex_boards/targets/xilinx_zc706.py

@@ -34,14 +34,18 @@ from litex.soc.cores.led import LedChaser
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.rst       = Signal()
-        self.cd_sys    = ClockDomain()
+        self.rst    = Signal()
+        self.cd_sys = ClockDomain()
 
         # # #
 
+        # Clk/Rst.
+        clk200 = platform.request("clk200")
+
+        # PLL.
         self.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(self.rst)
-        pll.register_clkin(platform.request("sysclk"), 200e6)
+        pll.register_clkin(clk200, 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
@@ -57,7 +61,7 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU102", **kwargs)
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
@@ -70,7 +74,7 @@ class BaseSoC(SoCCore):
 def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=xilinx_zc706.Platform, description="LiteX SoC on ZC706.")
-    parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock generator.")
+    parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
     args = parser.parse_args()
 
     soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict)