From fe67766fb72a6d6ffb712afdd70e119dad76e627 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Jan 2021 11:38:07 +0100 Subject: [PATCH] targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). --- litex_boards/targets/c10lprefkit.py | 2 +- litex_boards/targets/colorlight_5a_75x.py | 2 +- litex_boards/targets/de0nano.py | 2 +- litex_boards/targets/de10lite.py | 2 +- litex_boards/targets/de10nano.py | 2 +- litex_boards/targets/de1soc.py | 2 +- litex_boards/targets/de2_115.py | 2 +- litex_boards/targets/hadbadge.py | 2 +- litex_boards/targets/linsn_rv901t.py | 2 +- litex_boards/targets/minispartan6.py | 2 +- litex_boards/targets/mist.py | 2 +- litex_boards/targets/qmtech_ep4ce15.py | 2 +- litex_boards/targets/ulx3s.py | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index c91114e..2f8381e 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -78,7 +78,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC16M16(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 7e4a817..b5ae144 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -144,7 +144,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) if board == "5a-75e" and revision == "6.0": sdram_cls = M12L64322A sdram_size = 0x80000000 diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index efe4922..5dac1f0 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16160(sys_clk_freq, sdram_rate), diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 608e394..f742976 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -70,7 +70,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 49bb900..3a11f18 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if with_mister_sdram and not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C32M16(sys_clk_freq, sdram_rate), diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 0583ae9..45527a2 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -64,7 +64,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index bc61e9a..f5becc4 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -64,7 +64,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16320(self.clk_freq, "1:1"), diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 8733f67..f4c8a42 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -71,7 +71,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C32M8(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index d8505b6..232a984 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -65,7 +65,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = M12L64322A(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 6cc1231..452e8d6 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -78,7 +78,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C16M16(sys_clk_freq, sdram_rate), diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index a600ef1..bfeb960 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -70,7 +70,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC16M16(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index 7245081..b7b7662 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = IS42S16160(sys_clk_freq, sdram_rate), diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 74d8107..3f5811c 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),