f400179b5b
targets: Import all from litex.gen on all targets.
2023-02-23 09:09:33 +01:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
99e2f04ee5
Be friendlier about incompatible options.
...
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
2021-01-29 18:08:38 -07:00
0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
bd4e92ad13
targets: cleanup, uniformize build arguments between targets.
2020-11-12 11:46:00 +01:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
2e1a816d1f
pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
2020-05-29 10:41:35 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
...
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
22f18f618e
pano_logic_g2: move gmii_rst_n to _CRG.
2020-05-26 08:36:06 +02:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
...
Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
19b12fd984
targets/panol_logic_g2: replace with a minimal target.
2020-05-07 16:36:04 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Joey Bushagour
Gary Wong
Hans Baier
Skip Hansen