b2a346edc8
aliexpress_u420t: Review/Simplify.
...
Specific integrated ROM/SRAM/MAIN_RAM size can be passed through command line parameters.
2022-04-21 10:32:18 +02:00
3e9e970076
Add aliexpress prefix to boards from aliexpress that seem to be from the same unknown vendor.
2022-04-21 10:06:11 +02:00
8c51cb12c8
Merge pull request #383 from sysmanalex/master
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Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-21 10:02:05 +02:00
f986855926
Merge pull request #372 from mkj/butterstick-ethdelay
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butterstick: set ethernet rx_delay to 0ns
2022-04-21 09:00:13 +02:00
53e9e0914e
qmtech_ep4cgx150 80MHz default works well
2022-04-16 15:00:01 +07:00
b41d72e1d0
add board support for QMTech EP4CGX150
2022-04-16 06:36:24 +07:00
23b1b15486
Add initial/minimal Pluto SDR support.
2022-04-14 12:13:03 +02:00
1e00a43fdd
board u420t kintex update v0.2
2022-04-13 00:12:59 +03:00
89570b005c
Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-12 22:38:14 +03:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
867489d855
xilinx_zcu106: Add PCIe Gen3 X4 support.
2022-04-01 10:01:06 +02:00
13e5062793
Merge pull request #379 from chmousset/add_t8_devkit
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[enh] added efinix t8f81 dev kit
2022-03-28 14:58:21 +02:00
e6a9f44580
Merge pull request #378 from antmicro/add-missing-peripherals
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DDR4 datacenter: add missing peripherals
2022-03-28 14:40:22 +02:00
83d7c3fb39
Merge pull request #377 from Johnsel/arduino_mkrvidor4000
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Board support for Arduino MKR Vidor 4000
2022-03-28 14:34:59 +02:00
7a68dcc79b
[enh] added efinix t8f81 dev kit
2022-03-26 09:52:20 +01:00
33516a40f4
antmicro_datacenter: add missing peripherals
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 13:49:41 +01:00
77cb866233
antmicro_datacenter: add HDMI output
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 10:03:07 +01:00
901942bda6
Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================--
...
CPU:BUS:E 32-bit @ 4GiB
CSR:16-bit @ 48MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 21.3MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
2022-03-24 07:39:14 -07:00
c081177d77
pynq_z1/zybo_z7: Update .xci (With changes from #99 ).
2022-03-24 09:15:36 +01:00
bb974ae1af
decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support.
2022-03-23 15:24:49 +01:00
ce4b627e3c
targets: Remove l2_size workaround (no longer required).
2022-03-22 19:13:23 +01:00
2a206def0f
targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).
2022-03-22 17:32:35 +01:00
53c221a1fa
butterstick: set ethernet rx_delay to 0ns
...
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.
In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
2022-03-22 13:51:03 +08:00
b8b0aead28
Added basic support for Arduino MKR Vidor 4000
2022-03-21 18:54:29 -07:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
d90e260414
targets/digilent_atlys: Fix target.
2022-03-21 17:38:02 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
eb8657f515
gsd_orangecrab: Revert dm_remapping (Useful when built with VexRiscv-SMP and native LiteDRAM interface).
2022-03-18 12:56:13 +01:00
9faa805ab9
alinx_ax7010: Review/Cleanup.
2022-03-17 11:31:02 +01:00
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010
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Add ALINX AX7010 board support
2022-03-17 09:52:04 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:24:24 +08:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
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Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
adbcc2e547
add zcu102 target file
2022-03-16 15:55:37 +01:00
9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:51:13 +08:00
9c55773275
Add files via upload
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Add zynq_xc7z010 board support
2022-03-12 12:33:41 +08:00
9f9afeaafa
targets/nexys-video: Add support for sata pll refclk
2022-03-11 14:40:21 -05:00
3b74673a93
Merge pull request #363 from curliph/master
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add Gowin programmer support
2022-03-08 17:26:50 +01:00
f52a915487
lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer).
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I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5 .
Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 8 2022 15:34:22
BIOS CRC passed (c7fe9ecd)
Migen git sha1: ac70301
LiteX git sha1: 7ebc7625
--=============== SoC ==================--
CPU: FireV-STANDARD @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 23.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
2022-03-08 15:40:52 +01:00
39e4e211bb
targets/decklink_mini_4k: Add build/use instructions.
2022-03-08 14:14:18 +01:00
2df7fd573c
Update sipeed_tang_nano_9k.py
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Add Gowin programmer support
2022-03-08 14:04:28 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
ec28ca8fa3
adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
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This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.
Note that the PCIe support requires :
- Change the .xci in the litepcie to use the right Quad
- Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
timing constrainst of litepcie apply correctly
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-03 22:17:09 +01:00
0f2e13fdf7
sqrl_fk33: Add HBM2 support (from https://github.com/enjoy-digital/fk33_hbm2_test ).
2022-03-03 17:34:48 +01:00
99a66274c8
xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX.
2022-03-03 16:11:48 +01:00
b80c7a7843
targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required.
2022-03-03 15:50:53 +01:00
db2d83ea29
antmicro_datacenter: use 100 MHz and add i2c master
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:00:36 +01:00
0b80890119
antmicro_datacenter: add 1 cycle of latency for RCD IC
2022-03-01 12:43:08 +01:00
9976b47f72
antmicro_datacenter: generate outputs for rowhammer-tester
2022-03-01 12:43:08 +01:00
5359fc5bfc
antmicro_datacenter: use A7DDRPHY
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-03-01 12:43:08 +01:00
2c4d31066f
digilent_arty_z7: Defaults to no_uart.
2022-03-01 11:15:30 +01:00
673676e3cb
digilent_arty_a7: Switch to VivadoProgrammer.
2022-03-01 10:48:22 +01:00
1320f3bd23
Merge pull request #357 from DaveBerkeley/colorlight_i9
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Add ColorLight i9 v7.2
2022-03-01 10:07:55 +01:00
a19c03fa55
targets: Switch to generic/portable HyperRAM core from LiteX.
2022-03-01 09:10:19 +01:00
c9d009c735
Add ColorLight i9 v7.2
2022-02-28 14:08:49 +00:00
1623ba5942
targets/stlv7325: Reduce sys_clk_freq to 100MHz.
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See https://github.com/enjoy-digital/litedram/issues/285 .
2022-02-25 09:04:07 +01:00
872113e1cc
stlv7325: Add SDCard support.
2022-02-24 18:02:43 +01:00
a08f346d90
stlv7325: Add Etherbone support (untested).
2022-02-24 17:43:53 +01:00
b1550f006a
stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.
2022-02-24 17:17:08 +01:00
174d958ca7
Initial support for STLV7325 Kintex-7 board.
2022-02-23 18:28:55 +01:00
6661947d96
Merge pull request #354 from madscientist159/master
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Add initial support for RCS Arctic Tern boards
2022-02-23 18:06:08 +01:00
1717af68ac
targets/sqrl_acorn/ddr3: Disable write_latency_calibration.
...
Introduce some memtest failures on some boards.
2022-02-23 10:38:43 +01:00
ae4b3c0938
Add initial support for RCS Arctic Tern boards
2022-02-21 20:04:51 -06:00
85397818d9
add Xilinx ZCU216 support
2022-02-21 19:14:13 +01:00
7d84e6e863
efinix_titanium_ti60_t225: Add SPI/Native SDCard support.
...
Both modes working with 8559b88ad8
2022-02-21 10:35:06 +01:00
df36cdbcc9
siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax).
2022-02-18 11:47:08 +01:00
d85f88f42a
siglent_sds1104xe: Reduce DRAM's width to 16-bit for now (to use NaxRiscv).
2022-02-16 17:59:40 +01:00
08a79fa3ac
lattice_ecp5_vip: Minor cleanups, fix CI.
2022-02-15 10:58:38 +01:00
30afe26669
Merge pull request #348 from hubmartin/ecp5-vip
...
Draft: Add Lattice ECP5 VIP board + HDMI output board support
2022-02-15 08:53:57 +01:00
896884dd21
Merge branch 'master' into axu2cga_software
2022-02-15 08:21:29 +01:00
3f58df9974
platforms/targets: Fix typos.
2022-02-14 17:26:46 +01:00
5eca41ac73
targets/alinx_axu2cga: adding PS software support (inspired by xilinx_kv260)
2022-02-12 18:24:01 +01:00
d672d9a9b1
targets: s/alinx_axu2gca/alinx_axu2cga/gc
2022-02-12 18:12:45 +01:00
c2cd4410df
Code cleanup, add copyright
...
Signed-off-by: hubmartin <hub.martin@gmail.com>
2022-02-12 17:50:07 +01:00
c0e671919d
sqrl_acorn: Downgrade to SATA Gen1 for now (allow lower sys_clk_freq and enough for current tests).
2022-02-09 19:10:12 +01:00
d9b77c6f25
digilent_arty: Add --flash support.
2022-02-09 17:51:56 +01:00
4894926c40
xilinx_kv260: +x.
2022-02-09 16:01:51 +01:00
27b03df886
Add Lattice ECP5 VIP board + HDMI output board support
2022-02-08 21:47:58 +01:00
450a26f395
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2022-02-08 12:55:09 -05:00
7ed633dc4b
add guideline for serial interface
2022-02-08 12:54:34 -05:00
5a0f69502b
enable use of HBM for linux boot
2022-02-08 12:18:38 -05:00
18e8bec9d4
xilinx/kv260: Minor cleanup and add Build/Use instructions (from PR).
2022-02-07 08:12:43 +01:00
8621700916
Merge pull request #345 from sergachev/feature/xilinx_kv260
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Add Xilinx KV260 support
2022-02-07 07:53:55 +01:00
1d8c3789af
add Xilinx KV260 support
2022-02-06 14:38:57 +01:00
617fa26acd
Add 85F to help for orangecrab device
...
The 85F orangecrab board exists, and works fine when this option is set to 85F, but leaving it out of the help is a bit confusing.
2022-02-06 10:36:58 +00:00
346623fd06
trellisboard: Rename Video I2C to videoi2c.
2022-02-04 09:26:31 +01:00
6d4fe82179
trellisboard: Rename hdmi_i2c to i2c (to have access to i2c_scan in the BIOS).
2022-02-02 11:08:21 +01:00
0522d8b0c5
trellisboard: Update i2c.add_init call.
2022-02-02 10:59:54 +01:00
7f4d464f1b
trellisboard: Add Video Terminal/Framebuffer support and use new I2C init feature to automatically configure TP410 at startup.
2022-02-02 09:52:12 +01:00
4251cfa865
terasic_de0nano: Add Build/Use instructions with JTAG-UART.
2022-02-01 15:58:34 +01:00
4d45611935
targets: Replace JTAG Atlantic (Deprecated) with JTAG-UART.
2022-02-01 11:30:26 +01:00
9144cb44fb
Merge branch 'master' into jev/deca-eth
2022-01-31 16:22:58 +01:00
fbd424fc48
DECA: Add Ethernet and Etherbone support
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Also fixed pcf_en IO standard compared to golden Arrow project.
2022-01-29 15:15:53 -08:00
9e5224ca49
Add JTAGbone support to Terasic DECA
...
Along the way I added UARTbone support to DECA as well for debugging.
Examples:
./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load
litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg
litex_term crossover
./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load
litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
2022-01-27 14:13:58 -08:00
dd134a4b7d
digilent arty z7: allows toolchain selection (PL only)
2022-01-26 07:30:06 +01:00
74395ca80b
digilent_nexyx_video: Add default toolchain value to CRG (to avoid breaking existing designs).
2022-01-25 16:13:57 +01:00
624572f2e9
alinx_axu2gca: Review and do minor cosmetic changes.
2022-01-25 14:58:47 +01:00
537f04a13d
alinx_axu2gca: new board
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2022-01-25 07:35:42 +01:00
621d45cd9e
digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code.
...
sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.
2022-01-24 19:16:07 +01:00
Florent Kermarrec
Hans Baier
Alex Petrov
Alex Petrov
Charles-Henri Mousset
Alessandro Comodi
John Simons
Matt Johnston
Yonggang Liu
Joseph Faye
Gabriel Somlo
curliph
Sylvain Munaut
Piotr Binkowski
Karol Gugala
Dave Berkeley
Andrew Gillham
Raptor Engineering Development Team
Ilia Sergachev
Gwenhael Goavec-Merou
hubmartin
Sergiu Mosanu
Ben Stobbs
Jevin Sweval