73458ae9d7
decklink_quad_hdmi_recorder: Add Serial/UART pins.
2022-03-23 11:08:51 +01:00
d399f33dda
Merge pull request #374 from smunaut/adrv2crr
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adi_adrv2crr: Upgrade part to speedgrade 2
2022-03-23 09:09:57 +01:00
dc92584681
adi_adrv2crr: Upgrade part to speedgrade 2
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Even though the schematic and bom call for speedgrade 1, this was only for
the prototypes.
All productions units have been updated to speedgrade 2.
See this thread:
https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade
And the official HDL project for the board:
https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-22 23:36:41 +01:00
68c23e9251
faster sdcard boot on 2.0
2022-03-22 17:54:12 +01:00
3ebad7f7cc
gsd_orangecrab/butterstick: Add assert on devices.
2022-03-18 10:44:21 +01:00
9faa805ab9
alinx_ax7010: Review/Cleanup.
2022-03-17 11:31:02 +01:00
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010
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Add ALINX AX7010 board support
2022-03-17 09:52:04 +01:00
0f82db26da
rcs_artic_term_bmc_card: Fix is -> ==.
2022-03-17 09:45:47 +01:00
0e7145b4a1
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:21:42 +08:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
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Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
f4a48e51d7
add xilinx_zcu102 platform
2022-03-16 15:37:02 +01:00
5365c7fce4
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:50:09 +08:00
4159faf48b
Add files via upload
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Adding zynq_xc7z010 board support
2022-03-12 12:20:54 +08:00
688377de7c
lpddr4_test_board: Fix button pin
2022-03-11 15:59:43 +01:00
3b74673a93
Merge pull request #363 from curliph/master
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add Gowin programmer support
2022-03-08 17:26:50 +01:00
f52a915487
lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer).
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I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5 .
Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 8 2022 15:34:22
BIOS CRC passed (c7fe9ecd)
Migen git sha1: ac70301
LiteX git sha1: 7ebc7625
--=============== SoC ==================--
CPU: FireV-STANDARD @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 23.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
2022-03-08 15:40:52 +01:00
6eb906a2ca
Update sipeed_tang_nano_9k.py
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add Gowin programmer support
2022-03-08 14:00:53 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
cadfde4d39
litex_acorn_baseboard: Add SerDes refclk and m2_tx/rx pins.
2022-03-07 18:41:53 +01:00
50cc75fd56
Merge pull request #361 from smunaut/adrv2crr
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adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
2022-03-07 09:24:36 +01:00
37783ff9fd
colorlight_5a_75e: Fix _connectors_v6_0/j16 first pin (thanks @WhichWayWazzit).
2022-03-07 09:16:07 +01:00
ec28ca8fa3
adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
...
This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.
Note that the PCIe support requires :
- Change the .xci in the litepcie to use the right Quad
- Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
timing constrainst of litepcie apply correctly
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-03 22:17:09 +01:00
7933e9462e
antmicro_datacenter: fix i2c pads assignment
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 16:35:15 +01:00
7a5fe4c221
efinix_titanium_ti60_f225_dev_kit: Update iobank_info with the values used in the video example design.
2022-03-01 14:01:43 +01:00
db2d83ea29
antmicro_datacenter: use 100 MHz and add i2c master
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:00:36 +01:00
d6fddc746f
antmicro_datacenter: use single rank configuration
2022-03-01 12:43:08 +01:00
37905d1f34
antmicro_datacenter: use correct DQS pins
2022-03-01 12:43:08 +01:00
73b5143cec
antmicro_datacenter: add DCI_CASCADE
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-03-01 12:43:08 +01:00
0ceb15938f
digilent_arty_z7: Remove fake serial.
2022-03-01 11:05:59 +01:00
673676e3cb
digilent_arty_a7: Switch to VivadoProgrammer.
2022-03-01 10:48:22 +01:00
e16e5e0591
digilent_arty_z7: Fix add_period_constraint.
2022-03-01 10:30:14 +01:00
c9d009c735
Add ColorLight i9 v7.2
2022-02-28 14:08:49 +00:00
11dfe225fa
Merge pull request #356 from fjullien/add_mipi_tx
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efinix: add MIPI TX to platform Ti60
2022-02-25 16:53:11 +01:00
c54e92c47d
efinix: add MIPI TX to platform Ti60
2022-02-25 15:15:14 +01:00
b1550f006a
stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.
2022-02-24 17:17:08 +01:00
174d958ca7
Initial support for STLV7325 Kintex-7 board.
2022-02-23 18:28:55 +01:00
6661947d96
Merge pull request #354 from madscientist159/master
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Add initial support for RCS Arctic Tern boards
2022-02-23 18:06:08 +01:00
ae4b3c0938
Add initial support for RCS Arctic Tern boards
2022-02-21 20:04:51 -06:00
85397818d9
add Xilinx ZCU216 support
2022-02-21 19:14:13 +01:00
7d84e6e863
efinix_titanium_ti60_t225: Add SPI/Native SDCard support.
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Both modes working with 8559b88ad8
2022-02-21 10:35:06 +01:00
08a79fa3ac
lattice_ecp5_vip: Minor cleanups, fix CI.
2022-02-15 10:58:38 +01:00
30afe26669
Merge pull request #348 from hubmartin/ecp5-vip
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Draft: Add Lattice ECP5 VIP board + HDMI output board support
2022-02-15 08:53:57 +01:00
896884dd21
Merge branch 'master' into axu2cga_software
2022-02-15 08:21:29 +01:00
3f58df9974
platforms/targets: Fix typos.
2022-02-14 17:26:46 +01:00
b53b79821e
platforms: Expose toolchain parameter on all platforms to ease switching to alternative/open-source toolchains.
2022-02-14 11:35:18 +01:00
12b91eccdc
digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX).
2022-02-14 10:45:29 +01:00
50654f1b7b
platforms/alinx_axu2cga: add zynqmp PS configuration params
2022-02-12 18:19:55 +01:00
27b03df886
Add Lattice ECP5 VIP board + HDMI output board support
2022-02-08 21:47:58 +01:00
5d52bc5461
Fix seven_seg pin assignment in DE1-SoC
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Fixes quartus build error:
```
Error (171016): Can't place node "seven_seg5[6]" -- illegal location assignment PIN_AA2 File: /home/arusekk/src/fpga-proj/build/de1soc/gateware/de1soc.v Line: 49
```
2022-02-08 09:03:53 +01:00
18e8bec9d4
xilinx/kv260: Minor cleanup and add Build/Use instructions (from PR).
2022-02-07 08:12:43 +01:00
Florent Kermarrec
Sylvain Munaut
Goran Mahovlic
Yonggang Liu
Joseph Faye
Robert Szczepanski
curliph
Alessandro Comodi
Piotr Binkowski
Karol Gugala
Dave Berkeley
Franck Jullien
Andrew Gillham
Raptor Engineering Development Team
Ilia Sergachev
Gwenhael Goavec-Merou
hubmartin
Arusekk