#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2022 Icenowy Zheng # SPDX-License-Identifier: BSD-2-Clause from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.soc.cores.clock.gowin_gw2a import GW2APLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litex.soc.cores.video import * from liteeth.phy.rmii import LiteEthPHYRMII from litex_boards.platforms import sipeed_tang_primer_20k from litex.soc.cores.hyperbus import HyperRAM kB = 1024 mB = 1024*kB # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_video_pll=False): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_por = ClockDomain() # # # # Clk clk27 = platform.request("clk27") # PLL self.submodules.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device) pll.register_clkin(clk27, 27e6) pll.create_clkout(self.cd_sys, sys_clk_freq) # Power on reset (the onboard POR is not aware of reprogramming) por_count = Signal(16, reset=2**16-1) por_done = Signal() self.comb += self.cd_por.clk.eq(clk27) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.comb += pll.reset.eq(~por_done) # Video PLL if with_video_pll: self.submodules.video_pll = video_pll = GW2APLL(devicename=platform.devicename, device=platform.device) video_pll.register_clkin(clk27, 27e6) self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() video_pll.create_clkout(self.cd_hdmi5x, 125e6) self.specials += Instance("CLKDIV", p_DIV_MODE= "5", i_HCLKIN = self.cd_hdmi5x.clk, o_CLKOUT = self.cd_hdmi.clk ) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), with_spi_flash=False, with_led_chaser=True, with_video_terminal = False, with_ethernet = False, with_etherbone = False, eth_ip = "192.168.1.50", eth_dynamic_ip = False, **kwargs): platform = sipeed_tang_primer_20k.Platform() # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs) # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import W25Q32JV as SpiFlashModule from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1)) # Video ------------------------------------------------------------------------------------ if with_video_terminal: # FIXME: Un-tested. self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["r", "g", "b"]) self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi") #self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: # FIXME: Un-tested. from liteeth.phy.rmii import LiteEthPHYRMII self.submodules.ethphy = LiteEthPHYRMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), refclk_cd = None ) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, with_timing_constraints=False) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_timing_constraints=False) # Build -------------------------------------------------------------------------------------------- def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Primer 20K") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.") target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.") sdopts = target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).") target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") ethopts = target_group.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.") ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.") target_group.add_argument("--eth-ip", default="192.168.1.50", help="Etherbone IP address.") target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), with_spi_flash = args.with_spi_flash, with_video_terminal = args.with_video_terminal, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, eth_ip = args.eth_ip, eth_dynamic_ip = args.eth_dynamic_ip, **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) if args.build: builder.build() if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if args.flash: prog = soc.platform.create_programmer() prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"), external=True) if __name__ == "__main__": main()