#!/usr/bin/env python3 # # This file is part of LiteX-Boards. # # Copyright (c) 2020 Basel Sayeh # SPDX-License-Identifier: BSD-2-Clause from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import DDROutput from litex_boards.platforms import qmtech_ep4cex5 from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY from liteeth.phy.mii import LiteEthPHYMII # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() if sdram_rate == "1:2": self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain() else: self.clock_domains.cd_sys_ps = ClockDomain() if with_ethernet: self.clock_domains.cd_eth = ClockDomain() if with_vga: self.clock_domains.cd_vga = ClockDomain() # # # # Clk / Rst clk50 = platform.request("clk50") # PLL self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) if sdram_rate == "1:2": pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) # theoretically 90 degrees, but increase to relax timing pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) if with_ethernet: pll.create_clkout(self.cd_eth, 25e6) if with_vga: pll.create_clkout(self.cd_vga, 40e6) # SDRAM clock sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, variant="ep4ce15", sys_clk_freq=int(50e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, sdram_rate="1:1", **kwargs): platform = qmtech_ep4cex5.Platform(variant=variant, with_daughterboard=with_daughterboard) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet = with_ethernet or with_etherbone, with_vga = with_video_terminal or with_video_framebuffer, sdram_rate = sdram_rate ) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTECH EP4CE15" + (" + Daughterboard" if with_daughterboard else ""), **kwargs ) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build design.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--variant", default="ep4ce15", help="Board variant (ep4ce15 or ep4ce55).") target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.") ethopts = target_group.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.") target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") sdopts = target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") viopts = target_group.add_mutually_exclusive_group() viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( variant = args.variant, sys_clk_freq = int(float(args.sys_clk_freq)), with_daughterboard = args.with_daughterboard, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, eth_ip = args.eth_ip, eth_dynamic_ip = args.eth_dynamic_ip, with_video_terminal = args.with_video_terminal, with_video_framebuffer = args.with_video_framebuffer, sdram_rate = args.sdram_rate, **soc_core_argdict(args) ) if args.with_spi_sdcard: soc.add_spi_sdcard() if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) if args.build: builder.build() if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) if __name__ == "__main__": main()